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* gray code address for emiMatt Ettus2010-11-111-1/+7
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* fifo randomizer for emiMatt Ettus2010-11-115-4/+108
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* 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable ↵Ian Buckley2010-11-111-11/+11
| | | | | | full watermark 2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes.
* 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-112-9/+12
| | | | | | | | | | | | | | | which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles.
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-114-90/+169
| | | | | | | | | | Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
* Enhanced test bench to be more like real world applicationIan Buckley2010-11-112-7/+14
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* Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-11-113-9/+17
| | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
* capacity logic fixMatt Ettus2010-11-111-1/+1
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* Added capacity to the module pinoutIan Buckley2010-11-111-3/+4
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* Added a bunch of debug signals.Ian Buckley2010-11-112-3/+12
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* Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-11-113-226/+102
| | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
* Edited FIFO instance to delete port that was not regenerated after ↵Ian Buckley2010-11-111-1/+0
| | | | reconfiguration
* Found bug due to not accounting for the correct number of possible in flight ↵Ian Buckley2010-11-113-10/+60
| | | | | | | | | READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-11-119-79/+7073
| | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* Checkpoint checkin.Ian Buckley2010-11-119-0/+1013
| | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet.
* get it to buildMatt Ettus2010-11-114-5/+8
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* moved forward from the old branchMatt Ettus2010-11-116-0/+846
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