uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable fu...	Ian Buckley	2010-11-11	1	-11/+11
*	1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ	Ian Buckley	2010-11-11	2	-9/+12
*	Added external RAM FIFO to u2plus.	Ian Buckley	2010-11-11	4	-90/+169
*	Enhanced test bench to be more like real world application	Ian Buckley	2010-11-11	2	-7/+14
*	Corrected extfifo code so that all registers that are on SRAM signals are pac...	ianb	2010-11-11	3	-9/+17
*	capacity logic fix	Matt Ettus	2010-11-11	1	-1/+1
*	Added capacity to the module pinout	Ian Buckley	2010-11-11	1	-3/+4
*	Added a bunch of debug signals.	Ian Buckley	2010-11-11	2	-3/+12
*	Regenerated FIFO with lower trigger level for almost full flag to reflect log...	Ian Buckley	2010-11-11	3	-226/+102
*	Edited FIFO instance to delete port that was not regenerated after reconfigur...	Ian Buckley	2010-11-11	1	-1/+0
*	Found bug due to not accounting for the correct number of possible in flight ...	Ian Buckley	2010-11-11	3	-10/+60
*	External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...	Ian Buckley	2010-11-11	9	-79/+7073
*	Checkpoint checkin.	Ian Buckley	2010-11-11	9	-0/+1013
*	get it to build	Matt Ettus	2010-11-11	4	-5/+8
*	moved forward from the old branch	Matt Ettus	2010-11-11	6	-0/+846