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packed into IOBs
Explcit drives and skews added to GPIO pins
Corrected minor error in FIFO logic that showed data avail internally incorrectly
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current head UHD code.
Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
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Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.
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