uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵	Ian Buckley	2010-11-11	1	-0/+130
	current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.