| Commit message (Collapse) | Author | Age | Files | Lines |
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full watermark
2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes.
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Added code branch to ext_fifo.v using generate that instantiates
different input and out fifo's and touched nobl_fifo code so that it
works at 18 and 36bit widths.
Added 2nd DCM to top level to generate off chip RAMCLK.
Added explicit I/O instances to top level for tristate drivers and
changed signals to core as needed.
Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
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logic removed from nobl_fifo.
Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns.
Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads.
Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256
Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state.
Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
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There are problems with certain configurations it seems.
It is important that the fifo_xlnx_512x36_2clk_18to36 is
generated with the "almost_full" pin even though it is not used
in the application. if this pin is omitted the FPGA image doesn't
work correctly
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READ operations that can be in the extfifo pipeline.
Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept
in flight read data upon completion.
Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA
Still have to tackle making this simulate in Icarus
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current head UHD code.
Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
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Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.
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not attached yet
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