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There are problems with certain configurations it seems.
It is important that the fifo_xlnx_512x36_2clk_18to36 is
generated with the "almost_full" pin even though it is not used
in the application. if this pin is omitted the FPGA image doesn't
work correctly
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into ise12_efifo_work
Conflicts:
usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc
usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc
Resolving conflicts by regenerating files clenly in ISE12.1 coregen
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READ operations that can be in the extfifo pipeline.
Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept
in flight read data upon completion.
Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA
Still have to tackle making this simulate in Icarus
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current head UHD code.
Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
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Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.
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not attached yet
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