| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Adding in files that probably didn;t exist in the ISE10.1 version of coregen | Ian Buckley | 2010-08-12 | 5 | -0/+808 |
| * | Bringing all coregen files checked in into sync | Ian Buckley | 2010-08-12 | 10 | -137/+60 |
| * | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv in... | Ian Buckley | 2010-08-12 | 18 | -41/+587 |
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| | * | checkin of generated coregen files | Matt Ettus | 2010-08-11 | 18 | -8/+556 |
| * | | Found bug due to not accounting for the correct number of possible in flight ... | Ian Buckley | 2010-08-12 | 4 | -39/+53 |
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| * | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu... | Ian Buckley | 2010-07-31 | 4 | -15/+23 |
| * | Checkpoint checkin. | Ian Buckley | 2010-07-29 | 4 | -0/+494 |
| * | first attempt at cleaning up the build system | Matt Ettus | 2010-06-10 | 1 | -0/+19 |
| * | allow settings bus to cross to a new clock domain, should help timing, but no... | Matt Ettus | 2010-05-11 | 8 | -0/+514 |
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 48 | -0/+3055 |
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