| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
| |
|
|
|
|
|
| |
created new component wb_readback_mux_16LE.v for 16 wide bus
connected vita time pps to vita time controller and readbacks
|
|\
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
* u1e: (130 commits)
invert led signals because they are active low
duh
allow for CS to rise before, at the same time, or after OE
better debug pins
watch the ethernet chip select on our debug bus
fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift
send all gpmc signals to mictor
updated pins to match rev2, removed dip switch, etc. seems to compile ok.
pins are different on rev2
fixed makefile to compile with our new system
add register to tell host about compatibility level and which image we are using
move declaration to make loopback compile
no need for protocol headers since we're not doing ethernet
match the signal names in this design
debug pins cleanup
properly integrate the new tx chain
catch up with tx_policy
attach run_tx and run_rx to leds
connect atr
delay the q channel to make the channels line up on the AD9862
...
Conflicts:
usrp2/control_lib/Makefile.srcs
|
| |\
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
* ise12:
move declaration ahead of use
put run_tx and run_rx on the displayed LEDs
remove warnings
add mux and demux to build
mux multiple fifo streams into one. Allows priority or round robin
split fifo into 2 streams based on first line in each packet
precompute udp checksums
barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
|
| |\ \
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Made so Makefile changes as well to get it to build
* master:
new make works on ise12
produces good bin files
first attempt at cleaning up the build system
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
Conflicts:
usrp2/fifo/fifo36_to_fifo18.v
usrp2/top/u2_rev3/Makefile
usrp2/top/u2_rev3/Makefile.udp
usrp2/top/u2_rev3/u2_core_udp.v
|
| | | | |
|
| | | |
| | | |
| | | |
| | | | |
is LE.
|
| | | | |
|
| |\ \ \
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
* ise12_exp:
zero out debug pins. helps timing a little bit.
non-udp uses a different address for the tx dsp core
manual merge to use localparams from udp version
from UDP branch, changed names because I want these separate from the non-udp versions
ignore output files
new files from udp branch added to main Makefile
change the debug pins, which makes it more reliable. This is unnerving.
experimental mods to make ram loader fully synchronous. Based on IJB's work
fixes from IJB from 5/24. Basically connect unconnected wires.
removes the icache and pipelines the reads
|
| | |\ \ \
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
merge into udp version.
Raw ethernet, ISE 10 -- Passes timing, works
UDP, ISE 10 -- barely fails timing, works
ISE 12 -- both fail timing, not tested yet.
* new_ramloader:
experimental mods to make ram loader fully synchronous. Based on IJB's work
|
| | | | | | |
|
| | |\| | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Seems to work on raw ethernet version which was automatically merged
UDP version untested, and the following files were merged manually:
u2_core_udp.v
Makefile.udp
* master_nocache:
change the debug pins, which makes it more reliable. This is unnerving.
fixes from IJB from 5/24. Basically connect unconnected wires.
removes the icache and pipelines the reads
|
| | | | | | |
|
| | | | | | |
|
| |\ \ \ \ \
| | | |/ / /
| | |/| | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
* master:
get rid of some warnings by declaring setting reg width
added width parameter to avoid warnings (thanks IJB) and default value parameter
added pragmas suggested by Ian Buckley to help ISE12 synthesis
get rid of old CVS linkage
settings bus to dsp_clk now uses clock crossing fifo
remove files for old prototypes, they were confusing people
revert commit 9899b81f920 which should have improved timing but didn't
Conflicts:
usrp2/control_lib/setting_reg.v
usrp2/top/u2_core/u2_core.v
usrp2/top/u2_rev3/Makefile
|
| | | | | | |
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
(by design)
|
| | | | | | |
|
| | | | | | |
|
| | | | | | |
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
packet gen and test
|
| | | | | | |
|
| |\ \ \ \ \ |
|
| | | | | | | |
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
settings_bus_16 now handles variable address window sizes
split ctrl of nsgpio into ctrl (selector) and debug bits
|
| |\ \ \ \ \ \ |
|
| | | | | | | | |
|
| | | | | | | | |
|
| | | | | | | | |
|
| |\ \ \ \ \ \ \
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | | |
Conflicts:
.gitignore
|
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | | |
ISE chokes on the unequal size ram
|
| | | | | | | | | |
|
| | | | | | | | | |
|
| | | | | | | | | |
|
| | | | | | | | | |
|
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | | |
asserted. which is the point of a CE, but... it works.
Also committed latest bootloader, might not be final version.
|
| | | | | | | | | |
|
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | | |
has already incremented by the time the data is returned
|
| | | | | | | | | |
|
| | | | | | | | | |
|
| | | | | | | | | |
|
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | | |
unused write port on a ram
|
| | | | | | | | | |
|
| |_|_|_|_|_|_|/
|/| | | | | | | |
|
| |_|_|_|_|_|/
|/| | | | | |
| | | | | | |
| | | | | | | |
seem to work ok
|
| |_|_|_|_|/
|/| | | | | |
|
|\ \ \ \ \ \
| | |_|_|_|/
| |/| | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas
Conflicts:
usrp2/control_lib/setting_reg.v
usrp2/top/u2_core/u2_core.v
usrp2/top/u2_rev3/Makefile
|
| | | | | | |
|
| | |_|_|/
| |/| | | |
|