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* Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-012-212/+317
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| * Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵Matt Ettus2010-05-282-220/+252
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
| | * experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-262-220/+252
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| * | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-281-0/+73
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | * fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-0/+2
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| | * removes the icache and pipelines the readsMatt Ettus2010-05-201-0/+71
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| * | Merge branch 'master' into udpMatt Ettus2010-05-181-2/+4
| |\| | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | reverting logic clean up which should have made timing better, but made it ↵Matt Ettus2010-05-111-5/+12
| | | | | | | | | | | | worse instead
| * | Merge branch 'master' into udpMatt Ettus2010-05-112-13/+25
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| * \ \ Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-261-1/+1
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* | \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-271-2/+4
|\ \ \ \ \ | | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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| * | | | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
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* | | | test full width packetsMatt Ettus2010-05-241-0/+27
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* | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
| | | | | | | | | | | | | | | | (by design)
* | | | fix double declarationMatt Ettus2010-05-211-1/+0
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* | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-1/+1
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* | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-0/+24
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* | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-123-6/+48
| | | | | | | | | | | | | | | | packet gen and test
* | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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* | | | Merge branch 'master' into u1eMatt Ettus2010-05-123-14/+26
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| * | | cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
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| * | | allow settings bus to cross to a new clock domain, should help timing, but ↵Matt Ettus2010-05-111-0/+20
| | |/ | |/| | | | | | | not attached yet
| * | Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
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| * | | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
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* | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
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* | | | added 16-bit wide atr controllerMatt Ettus2010-04-013-14/+73
| | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
* | | | Merge branch 'udp' into u1eMatt Ettus2010-03-253-50/+51
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| * | | Merge branch 'master' into udpMatt Ettus2010-03-251-1/+1
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| * / | moved into subdirJosh Blum2010-01-2276-0/+11383
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* | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
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* | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
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* | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
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* | | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
|\| | | | | | | | | | | | | | Conflicts: .gitignore
| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
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* | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+44
| | | | | | | | ISE chokes on the unequal size ram
* | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-221-0/+54
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* | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
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* | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2276-0/+11382
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