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| * | | | | test full width packetsMatt Ettus2010-05-241-0/+27
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| * | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | (by design)
| * | | | | fix double declarationMatt Ettus2010-05-211-1/+0
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| * | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-1/+1
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| * | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-0/+24
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| * | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-123-6/+48
| | | | | | | | | | | | | | | | | | | | | | | | packet gen and test
| * | | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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| * | | | | Merge branch 'master' into u1eMatt Ettus2010-05-123-14/+26
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| * | | | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
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| * | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-013-14/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
| * | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-253-50/+51
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| * | | | | | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
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| * | | | | | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
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| * | | | | | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
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| * | | | | | | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: .gitignore
| * | | | | | | | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISE chokes on the unequal size ram
| * | | | | | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-221-0/+54
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| * | | | | | | | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
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| * | | | | | | | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
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* | | | | | | | | U2P: remember your semicolons.Nick Foster2010-10-071-1/+1
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* | | | | | | | | U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not ↵Nick Foster2010-10-071-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asserted. which is the point of a CE, but... it works. Also committed latest bootloader, might not be final version.
* | | | | | | | | quad uart instead of single, for the extra on board serial portsMatt Ettus2010-08-112-0/+72
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* | | | | | | | | proper selection of bank of ram for instruction, since the addressMatt Ettus2010-07-191-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | has already incremented by the time the data is returned
* | | | | | | | | reset the ack signalMatt Ettus2010-07-131-1/+1
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* | | | | | | | | attach the correct data portMatt Ettus2010-07-131-5/+5
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* | | | | | | | | separate boot ram, redone memory map, connected uartMatt Ettus2010-07-132-0/+247
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* | | | | | | | | ram_harvard2 is a workaround for a Xilinx bug that gets confused by an ↵Matt Ettus2010-07-122-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unused write port on a ram
* | | | | | | | | very slight mods from v5 versionMatt Ettus2010-07-121-0/+56
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* | | | | | | | | copied from quad radioMatt Ettus2010-07-121-0/+54
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* | | | | | | | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-143-212/+318
| |_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | seem to work ok
* | | | | | | first attempt at cleaning up the build systemMatt Ettus2010-06-1022-7528/+44
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* | | | | | Merge branch 'master' into udpMatt Ettus2010-05-181-2/+4
|\ \ \ \ \ \ | | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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| * | | | | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
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* | | | | reverting logic clean up which should have made timing better, but made it ↵Matt Ettus2010-05-111-5/+12
| | | | | | | | | | | | | | | | | | | | worse instead
* | | | | Merge branch 'master' into udpMatt Ettus2010-05-112-13/+25
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| * | | | cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
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| * | | | allow settings bus to cross to a new clock domain, should help timing, but ↵Matt Ettus2010-05-111-0/+20
| | | | | | | | | | | | | | | | | | | | not attached yet
* | | | | Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-261-1/+1
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| * | | Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
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| * | | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
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* | | Merge branch 'master' into udpMatt Ettus2010-03-251-1/+1
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| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
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| * Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2276-0/+11382
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* moved into subdirJosh Blum2010-01-2276-0/+11383
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