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* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-142-0/+74
| | | | | created new component wb_readback_mux_16LE.v for 16 wide bus connected vita time pps to vita time controller and readbacks
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1014-18/+623
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * u1e: (130 commits) invert led signals because they are active low duh allow for CS to rise before, at the same time, or after OE better debug pins watch the ethernet chip select on our debug bus fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift send all gpmc signals to mictor updated pins to match rev2, removed dip switch, etc. seems to compile ok. pins are different on rev2 fixed makefile to compile with our new system add register to tell host about compatibility level and which image we are using move declaration to make loopback compile no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy attach run_tx and run_rx to leds connect atr delay the q channel to make the channels line up on the AD9862 ... Conflicts: usrp2/control_lib/Makefile.srcs
| * Merge branch 'ise12' into u1eMatt Ettus2010-07-191-0/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet precompute udp checksums barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
| * \ Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-1421-7499/+47
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
| * | | left something out of the sensitivity list.Matt Ettus2010-06-101-1/+1
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| * | | added little endian capability for gpmc to fifo and fifo to gpmc, since ARM ↵Matt Ettus2010-06-062-37/+47
| | | | | | | | | | | | | | | | is LE.
| * | | get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-061-40/+0
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| * | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-012-212/+317
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | * \ \ Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵Matt Ettus2010-05-282-220/+252
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
| | | * | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-262-220/+252
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| | * | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-281-0/+73
| | |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | | * | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-0/+2
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| | | * | | removes the icache and pipelines the readsMatt Ettus2010-05-201-0/+71
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| * | | | | Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-271-2/+4
| |\ \ \ \ \ | | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | test full width packetsMatt Ettus2010-05-241-0/+27
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| * | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | (by design)
| * | | | | fix double declarationMatt Ettus2010-05-211-1/+0
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| * | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-1/+1
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| * | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-0/+24
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| * | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-123-6/+48
| | | | | | | | | | | | | | | | | | | | | | | | packet gen and test
| * | | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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| * | | | | Merge branch 'master' into u1eMatt Ettus2010-05-123-14/+26
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| * | | | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
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| * | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-013-14/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
| * | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-253-50/+51
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| * | | | | | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
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| * | | | | | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
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| * | | | | | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
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| * | | | | | | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: .gitignore
| * | | | | | | | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISE chokes on the unequal size ram
| * | | | | | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-221-0/+54
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| * | | | | | | | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
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| * | | | | | | | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
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* | | | | | | | | U2P: remember your semicolons.Nick Foster2010-10-071-1/+1
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* | | | | | | | | U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not ↵Nick Foster2010-10-071-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asserted. which is the point of a CE, but... it works. Also committed latest bootloader, might not be final version.
* | | | | | | | | quad uart instead of single, for the extra on board serial portsMatt Ettus2010-08-112-0/+72
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* | | | | | | | | proper selection of bank of ram for instruction, since the addressMatt Ettus2010-07-191-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | has already incremented by the time the data is returned
* | | | | | | | | reset the ack signalMatt Ettus2010-07-131-1/+1
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* | | | | | | | | attach the correct data portMatt Ettus2010-07-131-5/+5
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* | | | | | | | | separate boot ram, redone memory map, connected uartMatt Ettus2010-07-132-0/+247
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* | | | | | | | | ram_harvard2 is a workaround for a Xilinx bug that gets confused by an ↵Matt Ettus2010-07-122-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unused write port on a ram
* | | | | | | | | very slight mods from v5 versionMatt Ettus2010-07-121-0/+56
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* | | | | | | | | copied from quad radioMatt Ettus2010-07-121-0/+54
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* | | | | | | | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-143-212/+318
| |_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | seem to work ok
* | | | | | | first attempt at cleaning up the build systemMatt Ettus2010-06-1022-7528/+44
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* | | | | | Merge branch 'master' into udpMatt Ettus2010-05-181-2/+4
|\ \ \ \ \ \ | | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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| * | | | | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
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* | | | | reverting logic clean up which should have made timing better, but made it ↵Matt Ettus2010-05-111-5/+12
| | | | | | | | | | | | | | | | | | | | worse instead
* | | | | Merge branch 'master' into udpMatt Ettus2010-05-112-13/+25
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