aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2/control_lib
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | | | | | | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
| | | | | | | | |
* | | | | | | | | U2P: remember your semicolons.Nick Foster2010-10-071-1/+1
| | | | | | | | |
* | | | | | | | | U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not ↵Nick Foster2010-10-071-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asserted. which is the point of a CE, but... it works. Also committed latest bootloader, might not be final version.
* | | | | | | | | quad uart instead of single, for the extra on board serial portsMatt Ettus2010-08-112-0/+72
| | | | | | | | |
* | | | | | | | | proper selection of bank of ram for instruction, since the addressMatt Ettus2010-07-191-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | has already incremented by the time the data is returned
* | | | | | | | | reset the ack signalMatt Ettus2010-07-131-1/+1
| | | | | | | | |
* | | | | | | | | attach the correct data portMatt Ettus2010-07-131-5/+5
| | | | | | | | |
* | | | | | | | | separate boot ram, redone memory map, connected uartMatt Ettus2010-07-132-0/+247
| | | | | | | | |
* | | | | | | | | ram_harvard2 is a workaround for a Xilinx bug that gets confused by an ↵Matt Ettus2010-07-122-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unused write port on a ram
* | | | | | | | | very slight mods from v5 versionMatt Ettus2010-07-121-0/+56
| | | | | | | | |
* | | | | | | | | copied from quad radioMatt Ettus2010-07-121-0/+54
| |_|_|_|_|_|_|/ |/| | | | | | |
* | | | | | | | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-143-212/+318
| |_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | seem to work ok
* | | | | | | first attempt at cleaning up the build systemMatt Ettus2010-06-1022-7528/+44
| |_|_|_|_|/ |/| | | | |
* | | | | | Merge branch 'master' into udpMatt Ettus2010-05-181-2/+4
|\ \ \ \ \ \ | | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
| | | | | |
| * | | | | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
| | |_|_|/ | |/| | |
* | | | | reverting logic clean up which should have made timing better, but made it ↵Matt Ettus2010-05-111-5/+12
| | | | | | | | | | | | | | | | | | | | worse instead
* | | | | Merge branch 'master' into udpMatt Ettus2010-05-112-13/+25
|\| | | |
| * | | | cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
| | | | |
| * | | | allow settings bus to cross to a new clock domain, should help timing, but ↵Matt Ettus2010-05-111-0/+20
| | | | | | | | | | | | | | | | | | | | not attached yet
* | | | | Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-261-1/+1
|\| | | | | |_|_|/ |/| | |
| * | | Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
| |\ \ \ | | | |/ | | |/|
| * | | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
| | |/ | |/|
* | | Merge branch 'master' into udpMatt Ettus2010-03-251-1/+1
|\ \ \ | | |/ | |/|
| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
| |/
| * Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2276-0/+11382
|
* moved into subdirJosh Blum2010-01-2276-0/+11383
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 04:26:08 +0000