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* added a loopback control port, will do full wishbone interface laterMatt Ettus2011-05-261-0/+34
* N210: bootram expanded to 16KB (8 BRAMs) and UDP bootloader addedNick Foster2011-04-211-98/+143
* Merge branch 'master' into nextMatt Ettus2011-03-272-2/+2
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| * clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-162-2/+2
* | u2/u2p: reworked settings bus addressesMatt Ettus2011-03-161-3/+1
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* put these files in the right place. newfifo is long gone.Matt Ettus2011-02-168-256/+0
* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-261-0/+5
* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-142-0/+74
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1014-18/+623
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| * Merge branch 'ise12' into u1eMatt Ettus2010-07-191-0/+1
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| * \ Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-1421-7499/+47
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| * | | left something out of the sensitivity list.Matt Ettus2010-06-101-1/+1
| * | | added little endian capability for gpmc to fifo and fifo to gpmc, since ARM i...Matt Ettus2010-06-062-37/+47
| * | | get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-061-40/+0
| * | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-012-212/+317
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| | * \ \ Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual merg...Matt Ettus2010-05-282-220/+252
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| | | * | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-262-220/+252
| | * | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-281-0/+73
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| | | * | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-0/+2
| | | * | | removes the icache and pipelines the readsMatt Ettus2010-05-201-0/+71
| * | | | | Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-271-2/+4
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| * | | | | test full width packetsMatt Ettus2010-05-241-0/+27
| * | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (...Matt Ettus2010-05-211-1/+8
| * | | | | fix double declarationMatt Ettus2010-05-211-1/+0
| * | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-1/+1
| * | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-0/+24
| * | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-123-6/+48
| * | | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
| * | | | | Merge branch 'master' into u1eMatt Ettus2010-05-123-14/+26
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| * | | | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
| * | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-013-14/+73
| * | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-253-50/+51
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| * | | | | | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
| * | | | | | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
| * | | | | | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
| * | | | | | | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
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| * | | | | | | | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+44
| * | | | | | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-221-0/+54
| * | | | | | | | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
| * | | | | | | | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
* | | | | | | | | U2P: remember your semicolons.Nick Foster2010-10-071-1/+1
* | | | | | | | | U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not asser...Nick Foster2010-10-071-7/+10
* | | | | | | | | quad uart instead of single, for the extra on board serial portsMatt Ettus2010-08-112-0/+72
* | | | | | | | | proper selection of bank of ram for instruction, since the addressMatt Ettus2010-07-191-1/+5
* | | | | | | | | reset the ack signalMatt Ettus2010-07-131-1/+1
* | | | | | | | | attach the correct data portMatt Ettus2010-07-131-5/+5
* | | | | | | | | separate boot ram, redone memory map, connected uartMatt Ettus2010-07-132-0/+247
* | | | | | | | | ram_harvard2 is a workaround for a Xilinx bug that gets confused by an unused...Matt Ettus2010-07-122-0/+79
* | | | | | | | | very slight mods from v5 versionMatt Ettus2010-07-121-0/+56
* | | | | | | | | copied from quad radioMatt Ettus2010-07-121-0/+54
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