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* Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-271-2/+4
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| * added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
| * revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
* | test full width packetsMatt Ettus2010-05-241-0/+27
* | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (...Matt Ettus2010-05-211-1/+8
* | fix double declarationMatt Ettus2010-05-211-1/+0
* | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-1/+1
* | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-0/+24
* | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-123-6/+48
* | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
* | Merge branch 'master' into u1eMatt Ettus2010-05-123-14/+26
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| * cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
| * allow settings bus to cross to a new clock domain, should help timing, but no...Matt Ettus2010-05-111-0/+20
| * Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
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| * | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
* | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
* | | added 16-bit wide atr controllerMatt Ettus2010-04-013-14/+73
* | | Merge branch 'udp' into u1eMatt Ettus2010-03-253-50/+51
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| * \ \ Merge branch 'master' into udpMatt Ettus2010-03-251-1/+1
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| * / | moved into subdirJosh Blum2010-01-2276-0/+11383
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* | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
* | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
* | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
* | | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
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| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
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* | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+44
* | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-221-0/+54
* | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
* | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2276-0/+11382
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