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Commit message (Expand)AuthorAgeFilesLines
* reset the ack signalMatt Ettus2010-07-131-1/+1
* attach the correct data portMatt Ettus2010-07-131-5/+5
* separate boot ram, redone memory map, connected uartMatt Ettus2010-07-132-0/+247
* ram_harvard2 is a workaround for a Xilinx bug that gets confused by an unused...Matt Ettus2010-07-122-0/+79
* very slight mods from v5 versionMatt Ettus2010-07-121-0/+56
* copied from quad radioMatt Ettus2010-07-121-0/+54
* barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-143-212/+318
* first attempt at cleaning up the build systemMatt Ettus2010-06-1022-7528/+44
* Merge branch 'master' into udpMatt Ettus2010-05-181-2/+4
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| * added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
| * revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
* | reverting logic clean up which should have made timing better, but made it wo...Matt Ettus2010-05-111-5/+12
* | Merge branch 'master' into udpMatt Ettus2010-05-112-13/+25
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| * cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
| * allow settings bus to cross to a new clock domain, should help timing, but no...Matt Ettus2010-05-111-0/+20
* | Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-261-1/+1
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| * Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
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| * | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
* | | Merge branch 'master' into udpMatt Ettus2010-03-251-1/+1
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| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
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| * Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2276-0/+11382
* moved into subdirJosh Blum2010-01-2276-0/+11383
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