| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Merge branch 'master' into u1e_merge_with_master | Matt Ettus | 2010-05-27 | 1 | -2/+4 |
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile | ||||
| | * | added width parameter to avoid warnings (thanks IJB) and default value parameter | Matt Ettus | 2010-05-18 | 1 | -3/+5 |
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| | * | revert commit 9899b81f920 which should have improved timing but didn't | Matt Ettus | 2010-05-13 | 1 | -5/+13 |
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| * | | test full width packets | Matt Ettus | 2010-05-24 | 1 | -0/+27 |
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| * | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵ | Matt Ettus | 2010-05-21 | 1 | -1/+8 |
| | | | | | | | | | (by design) | ||||
| * | | fix double declaration | Matt Ettus | 2010-05-21 | 1 | -1/+0 |
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| * | | send bigger packets to reduce cpu load | Matt Ettus | 2010-05-20 | 1 | -1/+1 |
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| * | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rate | Matt Ettus | 2010-05-20 | 1 | -0/+24 |
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| * | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵ | Matt Ettus | 2010-05-12 | 3 | -6/+48 |
| | | | | | | | | | packet gen and test | ||||
| * | | add missing signal from sensitivity list | Matt Ettus | 2010-05-12 | 1 | -1/+1 |
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| * | | Merge branch 'master' into u1e | Matt Ettus | 2010-05-12 | 3 | -14/+26 |
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| | * | cleaned up the logic, this is copied over from quad radio | Matt Ettus | 2010-05-11 | 1 | -13/+5 |
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| | * | allow settings bus to cross to a new clock domain, should help timing, but ↵ | Matt Ettus | 2010-05-11 | 1 | -0/+20 |
| | | | | | | | | | not attached yet | ||||
| | * | Merge commit 'upstream/master' | Johnathan Corgan | 2010-03-09 | 1 | -1/+1 |
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| | * | | Fix missing item on sensitivity list | Johnathan Corgan | 2010-02-23 | 1 | -1/+1 |
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| * | | | packet generator and verifier, to test gpmc and other data transfer stuff | Matt Ettus | 2010-05-12 | 4 | -0/+153 |
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| * | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 3 | -14/+73 |
| | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits | ||||
| * | | | Merge branch 'udp' into u1e | Matt Ettus | 2010-03-25 | 3 | -50/+51 |
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| | * \ \ | Merge branch 'master' into udp | Matt Ettus | 2010-03-25 | 1 | -1/+1 |
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| | * / | | moved into subdir | Josh Blum | 2010-01-22 | 76 | -0/+11383 |
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| * | | | enable was on the wrong address pin, needs to be the highest order one | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
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| * | | | Switched xilinx primitives because they order the bits funny in the other one | Matt Ettus | 2010-02-25 | 1 | -48/+79 |
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| * | | | ISE chokes on the pure verilog version so we use the macro | Matt Ettus | 2010-02-25 | 1 | -4/+49 |
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| * | | | Merge branch 'master' into u1e | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
| |\| | | | | | | | | | | | | | | Conflicts: .gitignore | ||||
| | * | | proper initialization of the ram | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
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| * | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 1 | -0/+44 |
| | | | | | | | | | ISE chokes on the unequal size ram | ||||
| * | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 1 | -0/+54 |
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| * | | Modified nsgpio.v to support 16 bit little endian bus interface. | Matt Ettus | 2010-02-22 | 1 | -0/+124 |
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| * | | allow default uart clock divider | Matt Ettus | 2010-02-18 | 1 | -6/+7 |
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| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 76 | -0/+11382 |
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