| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵ | Matt Ettus | 2010-05-12 | 3 | -6/+48 |
| | | | | | packet gen and test | ||||
| * | add missing signal from sensitivity list | Matt Ettus | 2010-05-12 | 1 | -1/+1 |
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| * | Merge branch 'master' into u1e | Matt Ettus | 2010-05-12 | 3 | -14/+26 |
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| | * | cleaned up the logic, this is copied over from quad radio | Matt Ettus | 2010-05-11 | 1 | -13/+5 |
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| | * | allow settings bus to cross to a new clock domain, should help timing, but ↵ | Matt Ettus | 2010-05-11 | 1 | -0/+20 |
| | | | | | | | | | not attached yet | ||||
| | * | Merge commit 'upstream/master' | Johnathan Corgan | 2010-03-09 | 1 | -1/+1 |
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| | * | | Fix missing item on sensitivity list | Johnathan Corgan | 2010-02-23 | 1 | -1/+1 |
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| * | | | packet generator and verifier, to test gpmc and other data transfer stuff | Matt Ettus | 2010-05-12 | 4 | -0/+153 |
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| * | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 3 | -14/+73 |
| | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits | ||||
| * | | | Merge branch 'udp' into u1e | Matt Ettus | 2010-03-25 | 3 | -50/+51 |
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| | * \ \ | Merge branch 'master' into udp | Matt Ettus | 2010-03-25 | 1 | -1/+1 |
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| | * / | | moved into subdir | Josh Blum | 2010-01-22 | 76 | -0/+11383 |
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| * | | | enable was on the wrong address pin, needs to be the highest order one | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
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| * | | | Switched xilinx primitives because they order the bits funny in the other one | Matt Ettus | 2010-02-25 | 1 | -48/+79 |
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| * | | | ISE chokes on the pure verilog version so we use the macro | Matt Ettus | 2010-02-25 | 1 | -4/+49 |
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| * | | | Merge branch 'master' into u1e | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
| |\| | | | | | | | | | | | | | | Conflicts: .gitignore | ||||
| | * | | proper initialization of the ram | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
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| * | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 1 | -0/+44 |
| | | | | | | | | | ISE chokes on the unequal size ram | ||||
| * | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 1 | -0/+54 |
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| * | | Modified nsgpio.v to support 16 bit little endian bus interface. | Matt Ettus | 2010-02-22 | 1 | -0/+124 |
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| * | | allow default uart clock divider | Matt Ettus | 2010-02-18 | 1 | -6/+7 |
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| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 76 | -0/+11382 |
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