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* spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
| | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction.
* fifo ctrl: parameterize having a proto headerJosh Blum2012-03-161-5/+9
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* fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-162-9/+12
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* fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-162-7/+7
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* fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-162-13/+21
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* fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-162-19/+35
| | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
* spi: created simple spi core (sr based)Josh Blum2012-03-162-0/+196
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* fifo ctrl: simplified result packets (no tsf or sid)Josh Blum2012-03-161-16/+7
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* fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-161-90/+120
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* fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-162-5/+7
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* fifo ctrl: added time compare for timed commandsJosh Blum2012-03-161-3/+7
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* srb: created command queue, in and out state machinesJosh Blum2012-03-161-95/+160
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* usrp2: added vrt pack/unpacker to fifo ctrlJosh Blum2012-03-161-40/+107
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* usrp2: first pass implementation of fifo controlJosh Blum2012-03-162-0/+222
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* dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
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* dsp_rework: more thorough testMatt Ettus2012-01-311-8/+20
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* dsp: 8 to 16 bit conversion for tx side. believed to be functionalMatt Ettus2012-01-291-12/+36
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* dsp rework: integrated custom dsp module shellsJosh Blum2012-01-271-1/+1
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* dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-272-1/+65
| | | | added user registers into each toplevel (not used yet)
* forgot to add gpio atr to makefile source listJosh Blum2011-10-261-0/+1
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* u2/u2p: use new setting_reg based gpios, gets it off of wbMatt Ettus2011-10-261-0/+71
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* dsp_engine fix rst -> reset, default to read addressMatt Ettus2011-10-261-2/+2
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* dspengine: insert into the rx chainMatt Ettus2011-10-262-1/+3
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* dsp_engine: new way of doing DSP operations on VITA packets. Example does ↵Matt Ettus2011-10-263-0/+556
| | | | 16 to 8 bit conversion
* fix warning on dat_o in atr_controller16.vJosh Blum2011-08-291-3/+2
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* fix typoMatt Ettus2011-08-261-21/+21
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* all: tie unused ram inputs to 1 instead of zero, helps routingMatt Ettus2011-08-261-21/+21
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* usrp2: reconnect frontend calibration, timing meetsJosh Blum2011-08-261-2/+2
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* connect unused BRAM inputs to 1s to save routing logicJosh Blum2011-08-151-1/+1
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* u2: redo the atr gpio pins, remove some old cruftMatt Ettus2011-07-271-45/+31
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* appease the ISE godsMatt Ettus2011-07-192-2/+2
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* removed wb readback of ATR, allowing it to be synthesized as lutsMatt Ettus2011-07-192-4/+10
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* added copyrightsJosh Blum2011-06-0760-0/+1020
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* u1p: fix bus widths and other warningsMatt Ettus2011-05-261-11/+11
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* modernize the make files, it now compiles. not tested.Matt Ettus2011-05-261-0/+1
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* select bus is 2 bits wideNick Foster2011-05-261-1/+1
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* add padding into gpif response pathMatt Ettus2011-05-261-1/+7
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* pad out packets to a minimum lengthMatt Ettus2011-05-261-1/+10
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* fixed length command packetsMatt Ettus2011-05-261-1/+1
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* give response packets the same format as tx packetsMatt Ettus2011-05-261-1/+13
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* successful testMatt Ettus2011-05-261-0/+104
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* old and unusedMatt Ettus2011-05-261-151/+0
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* fifo to wb should be functionally complete, needs testingMatt Ettus2011-05-261-21/+141
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* added a loopback control port, will do full wishbone interface laterMatt Ettus2011-05-261-0/+34
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* N210: bootram expanded to 16KB (8 BRAMs) and UDP bootloader addedNick Foster2011-04-211-98/+143
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* Merge branch 'master' into nextMatt Ettus2011-03-272-2/+2
|\ | | | | | | | | | | | | * master: u2p: N200 Makefile u1e: use icarus verilog for lint clean up a bunch of warnings and incorrect bus widths
| * clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-162-2/+2
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* | u2/u2p: reworked settings bus addressesMatt Ettus2011-03-161-3/+1
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* put these files in the right place. newfifo is long gone.Matt Ettus2011-02-168-256/+0
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* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-261-0/+5
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