| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge branch 'ise12' into u1e | Matt Ettus | 2010-07-19 | 1 | -0/+1 |
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| | * | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all | Matt Ettus | 2010-06-14 | 3 | -212/+318 |
| * | | Merge branch 'master' into u1e_newbuild | Matt Ettus | 2010-06-14 | 21 | -7499/+47 |
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| | * | first attempt at cleaning up the build system | Matt Ettus | 2010-06-10 | 22 | -7528/+44 |
| * | | left something out of the sensitivity list. | Matt Ettus | 2010-06-10 | 1 | -1/+1 |
| * | | added little endian capability for gpmc to fifo and fifo to gpmc, since ARM i... | Matt Ettus | 2010-06-06 | 2 | -37/+47 |
| * | | get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bit | Matt Ettus | 2010-06-06 | 1 | -40/+0 |
| * | | Merge branch 'ise12_exp' into u1e | Matt Ettus | 2010-06-01 | 2 | -212/+317 |
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| | * \ | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual merg... | Matt Ettus | 2010-05-28 | 2 | -220/+252 |
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| | | * | | experimental mods to make ram loader fully synchronous. Based on IJB's work | Matt Ettus | 2010-05-26 | 2 | -220/+252 |
| | * | | | Merge branch 'master_nocache' into master_nocache_post_merge | Matt Ettus | 2010-05-28 | 1 | -0/+73 |
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| | | * | fixes from IJB from 5/24. Basically connect unconnected wires. | Matt Ettus | 2010-05-24 | 1 | -0/+2 |
| | | * | removes the icache and pipelines the reads | Matt Ettus | 2010-05-20 | 1 | -0/+71 |
| | * | | Merge branch 'master' into udp | Matt Ettus | 2010-05-18 | 1 | -2/+4 |
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| | * | | reverting logic clean up which should have made timing better, but made it wo... | Matt Ettus | 2010-05-11 | 1 | -5/+12 |
| | * | | Merge branch 'master' into udp | Matt Ettus | 2010-05-11 | 2 | -13/+25 |
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| | * \ \ | Merge branch 'corgan_fixes' into udp_corgan | Matt Ettus | 2010-04-26 | 1 | -1/+1 |
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| * | \ \ \ | Merge branch 'master' into u1e_merge_with_master | Matt Ettus | 2010-05-27 | 1 | -2/+4 |
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| | * | | | | added width parameter to avoid warnings (thanks IJB) and default value parameter | Matt Ettus | 2010-05-18 | 1 | -3/+5 |
| | * | | | | revert commit 9899b81f920 which should have improved timing but didn't | Matt Ettus | 2010-05-13 | 1 | -5/+13 |
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| * | | | | test full width packets | Matt Ettus | 2010-05-24 | 1 | -0/+27 |
| * | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (... | Matt Ettus | 2010-05-21 | 1 | -1/+8 |
| * | | | | fix double declaration | Matt Ettus | 2010-05-21 | 1 | -1/+0 |
| * | | | | send bigger packets to reduce cpu load | Matt Ettus | 2010-05-20 | 1 | -1/+1 |
| * | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rate | Matt Ettus | 2010-05-20 | 1 | -0/+24 |
| * | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet... | Matt Ettus | 2010-05-12 | 3 | -6/+48 |
| * | | | | add missing signal from sensitivity list | Matt Ettus | 2010-05-12 | 1 | -1/+1 |
| * | | | | Merge branch 'master' into u1e | Matt Ettus | 2010-05-12 | 3 | -14/+26 |
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| | * | | | cleaned up the logic, this is copied over from quad radio | Matt Ettus | 2010-05-11 | 1 | -13/+5 |
| | * | | | allow settings bus to cross to a new clock domain, should help timing, but no... | Matt Ettus | 2010-05-11 | 1 | -0/+20 |
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| | * | | Merge commit 'upstream/master' | Johnathan Corgan | 2010-03-09 | 1 | -1/+1 |
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| | * | | | Fix missing item on sensitivity list | Johnathan Corgan | 2010-02-23 | 1 | -1/+1 |
| * | | | | packet generator and verifier, to test gpmc and other data transfer stuff | Matt Ettus | 2010-05-12 | 4 | -0/+153 |
| * | | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 3 | -14/+73 |
| * | | | | Merge branch 'udp' into u1e | Matt Ettus | 2010-03-25 | 3 | -50/+51 |
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| | * | | | Merge branch 'master' into udp | Matt Ettus | 2010-03-25 | 1 | -1/+1 |
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| | * / | | moved into subdir | Josh Blum | 2010-01-22 | 76 | -0/+11383 |
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| * | | | enable was on the wrong address pin, needs to be the highest order one | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
| * | | | Switched xilinx primitives because they order the bits funny in the other one | Matt Ettus | 2010-02-25 | 1 | -48/+79 |
| * | | | ISE chokes on the pure verilog version so we use the macro | Matt Ettus | 2010-02-25 | 1 | -4/+49 |
| * | | | Merge branch 'master' into u1e | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
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| | * | | proper initialization of the ram | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
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| * | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 1 | -0/+44 |
| * | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 1 | -0/+54 |
| * | | Modified nsgpio.v to support 16 bit little endian bus interface. | Matt Ettus | 2010-02-22 | 1 | -0/+124 |
| * | | allow default uart clock divider | Matt Ettus | 2010-02-18 | 1 | -6/+7 |
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| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 76 | -0/+11382 |
