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path: root/usrp2/control_lib/Makefile.srcs
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* fpga: added setting regs based simple_i2c_coreJosh Blum2012-05-301-0/+1
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* fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-161-1/+1
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* spi: created simple spi core (sr based)Josh Blum2012-03-161-0/+1
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* usrp2: first pass implementation of fifo controlJosh Blum2012-03-161-0/+1
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* dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-271-1/+2
| | | | added user registers into each toplevel (not used yet)
* forgot to add gpio atr to makefile source listJosh Blum2011-10-261-0/+1
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* dspengine: insert into the rx chainMatt Ettus2011-10-261-0/+2
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* modernize the make files, it now compiles. not tested.Matt Ettus2011-05-261-0/+1
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* put these files in the right place. newfifo is long gone.Matt Ettus2011-02-161-5/+0
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* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-261-0/+5
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* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-141-0/+1
| | | | | created new component wb_readback_mux_16LE.v for 16 wide bus connected vita time pps to vita time controller and readbacks
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-101-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * u1e: (130 commits) invert led signals because they are active low duh allow for CS to rise before, at the same time, or after OE better debug pins watch the ethernet chip select on our debug bus fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift send all gpmc signals to mictor updated pins to match rev2, removed dip switch, etc. seems to compile ok. pins are different on rev2 fixed makefile to compile with our new system add register to tell host about compatibility level and which image we are using move declaration to make loopback compile no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy attach run_tx and run_rx to leds connect atr delay the q channel to make the channels line up on the AD9862 ... Conflicts: usrp2/control_lib/Makefile.srcs
| * Merge branch 'ise12' into u1eMatt Ettus2010-07-191-0/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet precompute udp checksums barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
| * | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
* | | quad uart instead of single, for the extra on board serial portsMatt Ettus2010-08-111-0/+1
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* | | separate boot ram, redone memory map, connected uartMatt Ettus2010-07-131-0/+1
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* | | ram_harvard2 is a workaround for a Xilinx bug that gets confused by an ↵Matt Ettus2010-07-121-0/+2
| |/ |/| | | | | unused write port on a ram
* | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-141-0/+1
|/ | | | seem to work ok
* first attempt at cleaning up the build systemMatt Ettus2010-06-101-0/+44
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