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* Added set time and set time at next pps. Removed the old sync pps commands, t...Josh Blum2010-01-181-2/+2
* remove time_sync and master_timer.Matt Ettus2010-01-182-22/+22
* allow processor to read back vrt time over readback muxMatt Ettus2010-01-181-2/+2
* proper time sync to ppsMatt Ettus2010-01-181-1/+1
* dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ...Matt Ettus2009-12-141-3/+3
* changed debug pins to see incoming dataMatt Ettus2009-12-121-3/+4
* fixed typo in u2_core.v resulting in unconnected net. added debug pinsMatt Ettus2009-12-111-11/+19
* First cut at vita tx, whole thing compilesMatt Ettus2009-12-092-27/+36
* forgot to declare wiresMatt Ettus2009-11-061-0/+4
* moved regs around for vita49Matt Ettus2009-11-051-4/+5
* vita rx instead of rx_control. Ready for firmware testing. Misses timing by...Matt Ettus2009-11-052-2/+25
* put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-052-1/+12
* This branch is for porting from the quad radio, and minor text cleanupsMatt Ettus2009-11-042-15/+32
* earliest beta files renamed to avoid confusionMatt Ettus2009-10-116-0/+0
* Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-011-1/+3
* fullchip sim now compiles again, after moving eth and models over to new simp...Matt Ettus2009-10-011-1/+1
* Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-301-82/+63
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| * Copied wb_1master back from quad radioMatt Ettus2009-09-301-81/+62
* | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
* | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-201-2/+2
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| * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-041-2/+2
* | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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* | Implement Eth flow control using pause framesMatt Ettus2009-09-041-0/+1
* | parameterized fifo sizes, some reformattingMatt Ettus2009-09-041-3/+2
* | debug the rx sideMatt Ettus2009-09-041-1/+6
* | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-031-3/+3
* | MAC transmit seems to work now. The root cause of the problem was accidental...Matt Ettus2009-09-031-39/+17
* | debug pins, cleaned ignoresMatt Ettus2009-09-022-8/+22
* | Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-312-90/+68
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* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-137-0/+257
* Add custom FPGA build.jcorgan2009-07-3012-41/+1704
* Fix swapped signals.jcorgan2009-04-272-2/+3
* Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 FPG...jcorgan2009-04-228-0/+776
* mostly formatting and name changes. commented out special purpose pins.matt2009-04-121-180/+180
* from u2p2, autogeneratedmatt2009-04-121-279/+353
* Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and strea...jcorgan2009-04-041-1/+1
* debug ports for fifo level testing. Normally I wouldn't check this in, but a...matt2009-04-021-3/+3
* remove support for unmodified dbsrx because there is way too much phase noise...matt2009-02-261-9/+1
* set all debug stuff to zeromatt2009-02-241-13/+10
* support for unmodified dbsrx boardsmatt2009-02-231-1/+9
* new cordicmatt2009-01-192-0/+2
* pps sync works, meets timingmatt2008-12-151-7/+5
* synchronized pps, lots of debug pins changed, works, meets timingmatt2008-12-141-49/+71
* hardware control of ledsmatt2008-11-091-2/+16
* u2_rev2 now works againmatt2008-10-231-1/+3
* make rev2 compile againmatt2008-10-221-1/+2
* New serdes status interrupt, clk_status interrupt. New capability to flush t...matt2008-10-112-4/+8
* added the basic wb<-->extram interface and a serdes interrupt to tell link st...matt2008-10-082-28/+53
* catch up with latest pin defs of u2_corematt2008-09-211-1/+3
* allow fpga to take over sd card interface from cpldmatt2008-09-172-9/+29
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