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* make it match the 36 bit wide versionMatt Ettus2010-01-141-2/+2
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* better debug pinsMatt Ettus2010-01-051-5/+6
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* place udp core in the memory spaceMatt Ettus2010-01-051-8/+11
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* Merge branch 'wip/usrp2' of http://gnuradio.org/git/matt into wip/usrp2Josh Blum2010-01-051-1/+1
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| * proper time sync to ppsMatt Ettus2009-12-221-1/+1
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* | Merge branch 'udp' of http://gnuradio.org/git/matt into wip/usrp2Josh Blum2010-01-052-4/+26
|\ \ | |/ |/| | | | | Conflicts: usrp2/fpga/top/u2_rev3/Makefile
| * barebones udp support. Compiles, but untested.Matt Ettus2009-12-212-4/+26
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* | dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ↵Matt Ettus2009-12-141-3/+3
| | | | | | | | vrt fixed
* | changed debug pins to see incoming dataMatt Ettus2009-12-121-3/+4
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* | fixed typo in u2_core.v resulting in unconnected net. added debug pinsMatt Ettus2009-12-111-11/+19
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* | First cut at vita tx, whole thing compilesMatt Ettus2009-12-092-27/+36
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* | forgot to declare wiresMatt Ettus2009-11-061-0/+4
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* | moved regs around for vita49Matt Ettus2009-11-051-4/+5
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* | vita rx instead of rx_control. Ready for firmware testing. Misses timing ↵Matt Ettus2009-11-052-2/+25
| | | | | | | | by a little bit, will worry later.
* | put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-052-1/+12
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* This branch is for porting from the quad radio, and minor text cleanupsMatt Ettus2009-11-042-15/+32
| | | | | | The counter is for performance monitoring in firmware, priority encoder and new interrupt controller are from quad radio and speed up interrupts. This is tested and it works for me.
* earliest beta files renamed to avoid confusionMatt Ettus2009-10-116-0/+0
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* Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-011-1/+3
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* fullchip sim now compiles again, after moving eth and models over to new ↵Matt Ettus2009-10-011-1/+1
| | | | simple_gemac
* Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-301-82/+63
|\ | | | | | | | | | | | | Functionality should not change at all Conflicts: usrp2/fpga/top/u2_core/u2_core.v
| * Copied wb_1master back from quad radioMatt Ettus2009-09-301-81/+62
| | | | | | | | more sane config options, should be exactly the same memory map
* | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
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* | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-201-2/+2
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| * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-041-2/+2
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* | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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* | Implement Eth flow control using pause framesMatt Ettus2009-09-041-0/+1
| | | | | | | | | | | | Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though.
* | parameterized fifo sizes, some reformattingMatt Ettus2009-09-041-3/+2
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* | debug the rx sideMatt Ettus2009-09-041-1/+6
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* | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-031-3/+3
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* | MAC transmit seems to work now. The root cause of the problem was ↵Matt Ettus2009-09-031-39/+17
| | | | | | | | accidentally using the rx_clk in one stage of the fifos on the tx side.
* | debug pins, cleaned ignoresMatt Ettus2009-09-022-8/+22
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* | Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-312-90/+68
|/ | | | | | | * svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz.
* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-137-0/+257
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* Add custom FPGA build.jcorgan2009-07-3012-41/+1704
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a custom build for USRP2 FPGA. It allows using a BasicRX or LFRX board and feed two independent, real signals. In addition, instead of the CIC/HB decimator, which optimizes frequency response, it uses an integrate and dump decimator, which optimizes for time-domain impulse response. These changes have been made in dsp_core_rx.v: * A second DDC has been added, sharing a frequency register with the existing DDC. * The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... into the receive FIFO. This limits the host configured decimation to 8 intead of 4. Use gr.deinterleave to recover the streams. * The ADCs are hardcoded: RX_A ==> DDC #1 I-input 0 ==> DDC #1 Q-input RX_B ==> DDC #2 I-input 0 ==> DDC #2 Q-input Thus, the input mux has been disabled. * The CIC/HB decimator has been replaced by an integrate and dump at the decimation rate. * To assist with meeting timing, the external RAM has been disabled. The basic application is to coherently sample two real IF streams and downconvert to baseband, while minimizing the impulse response duration of the resampling filters. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11519 221aa14e-8319-0410-a670-987f0aec2ac5
* Fix swapped signals.jcorgan2009-04-272-2/+3
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10926 221aa14e-8319-0410-a670-987f0aec2ac5
* Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 ↵jcorgan2009-04-228-0/+776
| | | | | | FPGA build to use integrate-and-dump decimator instead of CIC/HB combination. This provides a much shorter time duration impulse response for the same decimation rate, at the expense of worse stop-band rejection. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10888 221aa14e-8319-0410-a670-987f0aec2ac5
* mostly formatting and name changes. commented out special purpose pins.matt2009-04-121-180/+180
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10814 221aa14e-8319-0410-a670-987f0aec2ac5
* from u2p2, autogeneratedmatt2009-04-121-279/+353
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10813 221aa14e-8319-0410-a670-987f0aec2ac5
* Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and ↵jcorgan2009-04-041-1/+1
| | | | | | streaming GPIO functions for USRP2. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10766 221aa14e-8319-0410-a670-987f0aec2ac5
* debug ports for fifo level testing. Normally I wouldn't check this in, but ↵matt2009-04-021-3/+3
| | | | | | adding these ports actually improves timing. XST strikes again... git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10747 221aa14e-8319-0410-a670-987f0aec2ac5
* remove support for unmodified dbsrx because there is way too much phase ↵matt2009-02-261-9/+1
| | | | | | noise. only modified dbsrx are supported git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10521 221aa14e-8319-0410-a670-987f0aec2ac5
* set all debug stuff to zeromatt2009-02-241-13/+10
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10497 221aa14e-8319-0410-a670-987f0aec2ac5
* support for unmodified dbsrx boardsmatt2009-02-231-1/+9
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10482 221aa14e-8319-0410-a670-987f0aec2ac5
* new cordicmatt2009-01-192-0/+2
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10259 221aa14e-8319-0410-a670-987f0aec2ac5
* pps sync works, meets timingmatt2008-12-151-7/+5
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10120 221aa14e-8319-0410-a670-987f0aec2ac5
* synchronized pps, lots of debug pins changed, works, meets timingmatt2008-12-141-49/+71
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10118 221aa14e-8319-0410-a670-987f0aec2ac5
* hardware control of ledsmatt2008-11-091-2/+16
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9961 221aa14e-8319-0410-a670-987f0aec2ac5
* u2_rev2 now works againmatt2008-10-231-1/+3
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9831 221aa14e-8319-0410-a670-987f0aec2ac5
* make rev2 compile againmatt2008-10-221-1/+2
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9815 221aa14e-8319-0410-a670-987f0aec2ac5
* New serdes status interrupt, clk_status interrupt. New capability to flush ↵matt2008-10-112-4/+8
| | | | | | the ICache. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9779 221aa14e-8319-0410-a670-987f0aec2ac5
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