uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	tools: R&D testing prodecure updated for E3xx	Sugandha Gupta	2020-01-10	1	-25/+61
\| \| \| \| \| \|	-Adds embedded mode tests for E310 and E320 to the R&D testing procedure. -Modifies increased rates for 1Gige testing on E320
*	Tests: Fix subdev for N300 streaming tests	michael-west	2019-12-30	1	-6/+6
\| \| \| \|	Signed-off-by: michael-west <michael.west@ettus.com>
*	tools: typo in x3x0 dpdk fpga_funcverif test	mattprost	2019-12-17	1	-3/+3
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*	tools: update FPGA functional verification tests for X3x0 mcr's & dpdk	mattprost	2019-11-25	1	-82/+132
\| \| \| \| \| \| \|	-Added test cases for the 184.32MHz clock rate. -Removed some extra test cases for 200MHz clock rate in order to cut down on test time. -Added DPDK test cases (copied from 10gige and 2x_10gige test cases).
*	Docs: Adjust FPGA functional verification tests	michael-west	2019-10-15	1	-31/+30
\| \| \| \| \| \| \|	- Reduce long tests from 3600 seconds to 600 seconds. - Remove 2xRX@153.6e6 test for N310 10 GbE (not practical). Signed-off-by: michael-west <michael.west@ettus.com>
*	tools: Add FPGA functional verification tests for N32x	Alex Williams	2019-01-31	1	-0/+167
\| \| \| \| \| \| \|	This commit adds FPGA functional verification tests for all the N320 images. The tests follow a similar pattern to N310, but one additional category is present for using the DPDK transport. In order to use that test, the use_dpdk and mgmt_addr args must be specified in the options.
*	e320: Add R&D testing procedure	Sugandha Gupta	2018-09-24	1	-1/+84
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*	fixup! Testing: Add x300 Functional Verification	Vidush	2018-07-20	1	-1/+1
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*	Testing: Add x300 Functional Verification	Vidush	2018-06-15	1	-1/+131
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*	Test: Add HA,XA,WX Images	Vidush	2018-06-13	1	-0/+6
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*	Test: Run All Tests for Device and FPGA Image	Vidush	2018-06-13	1	-11/+34
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*	tools: Add a script for automated testing of FPGAFUNCVERIF	Martin Braun	2018-06-04	1	-0/+519