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* copied over from other eth corematt2009-04-044-0/+928
* made pause enabling a pin so we can set itmatt2009-04-032-5/+4
* Properly signals an error and drops the remainder of the packet if there is a...matt2009-04-021-6/+12
* more thorough tests, including overrun, underrun, crc err, etc.matt2009-04-021-34/+42
* simulate a hiccup in the filling of the fifo. If long enough, will cause a t...matt2009-04-021-0/+15
* test multiple error typesmatt2009-04-021-6/+30
* added a state to ensure the error signal propagates, and now we assert src_rd...matt2009-04-021-9/+13
* only write one error into fifomatt2009-04-021-1/+1
* generate error signalmatt2009-04-021-3/+3
* added error output line, alternative to simultaneous sof/eofmatt2009-04-021-6/+8
* logic to interface locallink fifos to our macmatt2009-04-025-77/+264
* add fifos to interface to the macsmatt2009-04-011-8/+46
* rx seems to work. haven't test error framesmatt2009-04-012-40/+192
* address filteringmatt2009-04-011-3/+9
* only report result for 1 cyclematt2009-04-011-0/+1
* variable length delay line, based on srl16matt2009-04-011-0/+21
* now checks the crc as well for the received sidematt2009-04-011-2/+5
* checkpointmatt2009-04-011-0/+34
* we now inhibit our own sending when a received pause frame comes. _rx.v is c...matt2009-03-315-14/+66
* sample packetmatt2009-03-311-0/+66
* cleaned up a littlematt2009-03-312-38/+32
* tx should be fully working nowmatt2009-03-312-26/+34
* everything but CRCmatt2009-03-312-17/+37
* nearly therematt2009-03-312-42/+134
* work in progress on a simpler gigabit-only macmatt2009-03-306-0/+527