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* try a width that works...Matt Ettus2010-01-141-1/+2
* try proper resetMatt Ettus2010-01-141-1/+1
* forgot to declare wireMatt Ettus2010-01-141-1/+3
* debug stateMatt Ettus2010-01-143-5/+12
* empty file, it is actually located in the control directoryMatt Ettus2010-01-141-0/+0
* make it match the 36 bit wide versionMatt Ettus2010-01-141-4/+6
* better debug pinsMatt Ettus2010-01-051-4/+3
* never should have checked in this generated binary fileMatt Ettus2009-12-211-21251/+0
* barebones udp support. Compiles, but untested.Matt Ettus2009-12-211-14/+15
* 19 bit wide interface in prep for connection to UDP/IP state machines.Matt Ettus2009-12-215-0/+21717
* Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-014-6/+10
* remove unused portMatt Ettus2009-09-101-1/+1
* might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
* Implement Eth flow control using pause framesMatt Ettus2009-09-044-73/+65
* parameterized fifo sizes, some reformattingMatt Ettus2009-09-041-51/+55
* allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
* MAC transmit seems to work now. The root cause of the problem was accidental...Matt Ettus2009-09-032-18/+30
* misc ignoresMatt Ettus2009-09-031-0/+2
* bring the testbench files up to dateMatt Ettus2009-09-023-87/+78
* debug pins, cleaned ignoresMatt Ettus2009-09-021-1/+0
* sort out active-low lines on locallink fifos, added debug pinsMatt Ettus2009-09-021-3/+15
* fixed addressing of registers, and added write enables to those that were mis...Matt Ettus2009-09-011-6/+9
* Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-318-60/+428
* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-131-0/+3
* basic wrapper workingmatt2009-04-043-9/+240
* first cut at a wishbone interface and wrapping the corematt2009-04-044-6/+221
* copied over from other eth corematt2009-04-044-0/+928
* made pause enabling a pin so we can set itmatt2009-04-032-5/+4
* Properly signals an error and drops the remainder of the packet if there is a...matt2009-04-021-6/+12
* more thorough tests, including overrun, underrun, crc err, etc.matt2009-04-021-34/+42
* simulate a hiccup in the filling of the fifo. If long enough, will cause a t...matt2009-04-021-0/+15
* test multiple error typesmatt2009-04-021-6/+30
* added a state to ensure the error signal propagates, and now we assert src_rd...matt2009-04-021-9/+13
* only write one error into fifomatt2009-04-021-1/+1
* generate error signalmatt2009-04-021-3/+3
* added error output line, alternative to simultaneous sof/eofmatt2009-04-021-6/+8
* logic to interface locallink fifos to our macmatt2009-04-025-77/+264
* add fifos to interface to the macsmatt2009-04-011-8/+46
* rx seems to work. haven't test error framesmatt2009-04-012-40/+192
* address filteringmatt2009-04-011-3/+9
* only report result for 1 cyclematt2009-04-011-0/+1
* variable length delay line, based on srl16matt2009-04-011-0/+21
* now checks the crc as well for the received sidematt2009-04-011-2/+5
* checkpointmatt2009-04-011-0/+34
* we now inhibit our own sending when a received pause frame comes. _rx.v is c...matt2009-03-315-14/+66
* sample packetmatt2009-03-311-0/+66
* cleaned up a littlematt2009-03-312-38/+32
* tx should be fully working nowmatt2009-03-312-26/+34
* everything but CRCmatt2009-03-312-17/+37
* nearly therematt2009-03-312-42/+134