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configurable number of clock ticks, to allow users to precisely align their T/R output with the pipeline delays in the transmitter.
There are two new registers:
FR_ATR_TX_DELAY (7'd2)
FR_ATR_RX_DELAY (7'd3)
...and the corresponding db_base.py methods to set them:
db_base.set_atr_tx_delay(clock_ticks)
db_base.set_atr_rx_delay(clock_ticks)
These methods are inherited by all the daughterboard objects so you can
call them from your scripts as:
subdev.set_atr_tx_delay(...)
...where 'subdev' represents the daughtercard object you're working with.
The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%,
with no additional synthesis messages or impact on timing.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5
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decimator so that signals are now roughly leveled, independent of the decimation rate. Decimating by 44 now works too ;)
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4848 221aa14e-8319-0410-a670-987f0aec2ac5
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signal processing pipeline when the Tx FIFO is empty.
This results in the DACs outputing zeros when there's no data, unless
the tx pipeline is disabled on the host.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4287 221aa14e-8319-0410-a670-987f0aec2ac5
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post-ADC / pre-DDC digital rssi measurement code.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3667 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3534 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
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