| Commit message (Collapse) | Author | Age | Files | Lines |
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Without this patch, the N320 code will rely on an error to occur to
determine the non-existence of the N321 LO distribution board. While
this works, it forces an error message where there's no error. This will
first check for the existence of the board before trying to initialize
it.
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Hardware revision was increased due to new firmware. No software
changes are required.
Signed-off-by: michael-west <michael.west@ettus.com>
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Remove unused variable data_word that never gets set,
but never read.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Remove unused 'coerced_value' variable since nobody reads
it ever.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Issue: Current code loads FPGA too early while many
essential peripherals such as net clocks are not brought up.
This change will make sure those are got init before FPGA loaded.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
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Add an argument to the UDP xport_mgr to adjust the xport sorting. This
enables Rhodium to use a different limit from Magnesium. Previously, the
sorting method would overload a link with both of Rhodium's higher-rate
streams.
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Fixes Rhodium for changes introduced in b7bab6a. The constructor call
for BfrfsEEPROM didn't match the signature, and Rhodium's EEPROM map
referred to the wrong revision.
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Remove some semicolons and superfluous imports.
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In bridge mode, packets may be arriving at the Ethernet device which
aren't meant for this device, and thus need different routing
instructions.
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Applying formatting changes to all .cpp and .hpp files in the following
directories:
```
find host/examples/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/tests/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/dboard/neon/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/dboard/magnesium/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/device3/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/mpmd/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/x300/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/utils/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find mpm/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
```
Also formatted host/include/, except Cpp03 was used as a the language
standard instead of Cpp11.
```
sed -i 's/ Cpp11/ Cpp03/g' .clang-format
find host/include/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
```
Formatting style was designated by the .clang-format file.
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- Add default bandwidth range
- Add default mash order constant
- Delete MPM todos
- Cleanup whitespace in MPM python code
- Add docstring for is_lo_dist_present
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Add method to generate GPGGA sensor data in MPM devices. This needs to
be constructed from TPV and SKY sensor data, and matches the GPGGA
sensor functionality in gpsd_iface.cpp.
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Affects Magnesium and Rhodium classes, which where duplicating this
code.
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- correct lmk initialization parameters
- adding missing parameters and consts wrt clock synchronization.
- fixed default master clock rate
- eiscat, ddc: update xml.
- remove references to CORDIC_FREQ in ddc_eiscat
- update readback reg addr in radio_eiscat
- set default spp from 3992 to 3968.
- updated jesd mode sequence initialization
- updating eiscat_radio_ctrl_impl
- add rx_codecs to property tree to display correct ADC chip.
- updated issue_stream_cmd
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If we use threading, the claimer loop's thread won't get scheduled in a
timely manner on n3xx. Using multiprocessing frees the claimer loop from
using the same GIL and gives back timely reclaim calls.
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- output 11 is unused, a value of 0 will leave the polarity as normal
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Return value should be fpga image type and not
sfp type, fixes a bug with uhd_image_loader while
trying to update XG and AA images
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The n321 overlay is no longer needed. The devices have been added to the
n320 overlay because the kernel cannot tear down multiple overlays
reliably.
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Previously, the init() procedure of the n3xx class passed either
the user-provided or the default clock_source and time_source values
to initialize the clocking configuration.
When the user did not provide these parameters, the default values
were assigned, overriding whatever configuration the device was
previously initialized with. Therefore, a dboard reinit was forced
when the currently configured state of the N3xx device did not match
the default configuration (i.e. internal sources).
Now, the init() procedure still provides the clock_source and
time_source values; but, if the user does not provide the
parameters, the previously used values are assigned (i.e.
self._clock_source and/or self._time_source).
By the time MPM runs this n3xx init() procedure for the first time,
both self._clock_source and self._time_source have been initialized
with the default internal values anyways in the
_init_ref_clock_and_time() procedure.
This change prevents additional, unnecessary calls to the
set_sync_source() procedure, which ultimately causes a daughterboard
reinitialization when either a new clock or time source is requested.
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The update_ref_clock_freq() procedure now updates the self._init_args
value of the Rhodium class daugtherboard objects in MPM to propagate
the latest user-selected arguments for future reference.
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Also updates our coding style file.
Ancient CMake versions required upper-case commands. Later command
names became case-insensitive. Now the preferred style is lower-case.
Run the following shell code (with GNU compliant sed):
cmake --help-command-list | grep -v "cmake version" | while read c; do
echo 's/\b'"$(echo $c | tr '[:lower:]' '[:upper:]')"'\(\s*\)(/'"$c"'\1(/g'
done > convert.sed \
&& git ls-files -z -- bootstrap '*.cmake' '*.cmake.in' \
'*CMakeLists.txt' | xargs -0 gsed -i -f convert.sed && rm convert.sed
(Make sure the backslashes don't get mangled!)
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gps_locked should be a bool not int.
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gpsd connection is not reliable.
Adding more error handling to re-connect during polling.
Add control flows to get_gps_time in order to give an effect of getting
the value on pps edge.
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This will release the i2c device when it's not in use. If MPM hangs on
to the i2c devices, we won't be able to cleanly change FPGA images--The
kernel hangs up the process until the refcount drops to zero.
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This function grabs the i2c character device path from the OF_NAME
property. That property must be unique in the device tree!
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- This is a combination of 5 commits.
- rh: add lo distribution board gpio expander
- rh: add lo distribution mpm functions
- rh: add code to conditionally initialize lo distribution
- rh: change empty i2c device from exception to assertion
- rh: add lo distribution board control
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- Improves spur performance
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- Confirmed the Phase DAC to be initialized at mid-scale.
- Confirmed the Phase DAC step resolution for fine clock shifting.
The clock synchronization algorithm relies on the Phase DAC to fine
shift the sampling clocks on each daughterboard.
Only a certain number of DAC codes are required for the actual clock
adjustment, thus a different range of codes may be chosen by
initializing the Phase DAC with a given value. With the selected range,
one may measure the Phase DAC's linearity and step resolution, which
defines how many steps are required when performing the fine shifting
of the clocks.
After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and
75%; it was found that the clock distribution PLL locks relatively
faster when using mid-scale (2^15). By testing the Phase DAC's
linearity, it was confirmed that the circuit resolution is 1.11 ps per
code.
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- Optimized JESD204B RX/TX links' latency.
- Made JESD latency constant across supported frequencies.
- Checking RX SYSREF capture in the FPGA deframer block.
The JESD204B standard can be linked in such a way to produce a
repeatable, deterministic delay from the framer to deframer. This is
accomplished by setting up a LMFC (local multiframe clock) in both
devices.
The LMFCs are reset whenever a SYSREF edge is captured by the framer
and deframer. Therefore, it is simple to control the LMFC rising edges
in each device by implementing variable delay elements on the SYSREF
pulses to the framer and deframer.
Latency across the JESD204B TX/RX links should remain constant and
deterministic across the supported sampling_clock_rate values. By
testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with
different delay values in the FPGA, one may decrease the latency and
provide enough setup and hold margin for the data to be transfered
through each JESD link.
It was found that a different set of SYSREF delay values are required
for sampling_clock_rate = 400 MSPS to match the latency of the other
supported rates.
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Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ni.com>
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This allows sharing mutexes between C++ and Python, and uses the with
statement to provide a locked-out context.
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Add coercing behavior to set_time_source and set_clock_source to
a valid sync source. Also, skip set_sync_source if device already
set to the corresponding one.
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