| Commit message (Collapse) | Author | Age | Files | Lines |
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Also updates our coding style file.
Ancient CMake versions required upper-case commands. Later command
names became case-insensitive. Now the preferred style is lower-case.
Run the following shell code (with GNU compliant sed):
cmake --help-command-list | grep -v "cmake version" | while read c; do
echo 's/\b'"$(echo $c | tr '[:lower:]' '[:upper:]')"'\(\s*\)(/'"$c"'\1(/g'
done > convert.sed \
&& git ls-files -z -- bootstrap '*.cmake' '*.cmake.in' \
'*CMakeLists.txt' | xargs -0 gsed -i -f convert.sed && rm convert.sed
(Make sure the backslashes don't get mangled!)
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gps_locked should be a bool not int.
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gpsd connection is not reliable.
Adding more error handling to re-connect during polling.
Add control flows to get_gps_time in order to give an effect of getting
the value on pps edge.
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This will release the i2c device when it's not in use. If MPM hangs on
to the i2c devices, we won't be able to cleanly change FPGA images--The
kernel hangs up the process until the refcount drops to zero.
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This function grabs the i2c character device path from the OF_NAME
property. That property must be unique in the device tree!
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- This is a combination of 5 commits.
- rh: add lo distribution board gpio expander
- rh: add lo distribution mpm functions
- rh: add code to conditionally initialize lo distribution
- rh: change empty i2c device from exception to assertion
- rh: add lo distribution board control
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- Improves spur performance
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- Confirmed the Phase DAC to be initialized at mid-scale.
- Confirmed the Phase DAC step resolution for fine clock shifting.
The clock synchronization algorithm relies on the Phase DAC to fine
shift the sampling clocks on each daughterboard.
Only a certain number of DAC codes are required for the actual clock
adjustment, thus a different range of codes may be chosen by
initializing the Phase DAC with a given value. With the selected range,
one may measure the Phase DAC's linearity and step resolution, which
defines how many steps are required when performing the fine shifting
of the clocks.
After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and
75%; it was found that the clock distribution PLL locks relatively
faster when using mid-scale (2^15). By testing the Phase DAC's
linearity, it was confirmed that the circuit resolution is 1.11 ps per
code.
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- Optimized JESD204B RX/TX links' latency.
- Made JESD latency constant across supported frequencies.
- Checking RX SYSREF capture in the FPGA deframer block.
The JESD204B standard can be linked in such a way to produce a
repeatable, deterministic delay from the framer to deframer. This is
accomplished by setting up a LMFC (local multiframe clock) in both
devices.
The LMFCs are reset whenever a SYSREF edge is captured by the framer
and deframer. Therefore, it is simple to control the LMFC rising edges
in each device by implementing variable delay elements on the SYSREF
pulses to the framer and deframer.
Latency across the JESD204B TX/RX links should remain constant and
deterministic across the supported sampling_clock_rate values. By
testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with
different delay values in the FPGA, one may decrease the latency and
provide enough setup and hold margin for the data to be transfered
through each JESD link.
It was found that a different set of SYSREF delay values are required
for sampling_clock_rate = 400 MSPS to match the latency of the other
supported rates.
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Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ni.com>
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This allows sharing mutexes between C++ and Python, and uses the with
statement to provide a locked-out context.
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Add coercing behavior to set_time_source and set_clock_source to
a valid sync source. Also, skip set_sync_source if device already
set to the corresponding one.
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This could lead to a less-restricted implementation for use in Python.
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This change to add skip_rfic as an device argument.
skip_rfic should be only used in ref_clock bist tests
to bring down the test time.
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- Allow generic path names to be given for each search parameter instead of
only checking the label
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This commit contains whitespace and formatting changes only. No
functional changes.
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Summary:
This change will allow correct args to pass from mboard to dboards,
that in turn can be useful for dboard manager.
Details:
In N310, the dboard manager needs the time source to be updated before
calling update_ref_clock_source(), because it will trigger a reinit of
the dboard, for which the time_source is essential to determine correct
clock synchronizer settings.
The special case is the white rabbit time source needs a different
internal ref_clock_frequency for the clock synchronizer than the passed
in ref_clock_freq.
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This provides a new utility for MPM devices (usrp_update_fs.py), which
goes through all the necessary steps to update a filesystem.
Will trigger a mender update, but the tool is not specific to Mender
and can be changed to use other methods in the future.
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N3xx and E320 were registering GPSDIface names as get_*_sensor instead
of just the sensor name. Fixing this to now register the sensor name.
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A value of 0 for dt-compat would cause db-init to use the rev
instead. This fixes the check to be on number of args instead of
the dt-compat value.
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When reloading the Periph Manager (as when we run the image loader),
we need to run the RPCServer `__init__` function in order to reset the
cache of RPC methods. Otherwise, that cache keeps stale references to
old functions (and prevents garbage collection).
It may be possible to reset the method cache some other way, but the
`_methods` attribute of RPCServer is Cython, and doesn't seem to be
accessible in our Python code.
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Adding MPM Git hash and version to the MPM device info. This
information is currently only available through logs when MPM starts
(it is the first log message in usrp_hwd.py). Adding it to the device
info makes it accessible to any application which checks that, such as
uhd_usrp_probe.
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This sequence is the one as described by the AD9371 user guide.
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- Returns true if the link of sfp0 is up (1G/10G)
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- For different ref clock frequencies, the ref_counter should change
and not the n_counter.
- The charge pump should be set to normal mode and tristate as that
would prevent the PLL to lock.
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- ref_clock_(int/ext) test was not changing adf400x driver settings
for new ref clock frequency. Therefore, changed the implementation
to use uhd_usrp_probe --sensor to set clock_source and get
'ref_locked' sensor value
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