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* rh: change uio access to utilize with-asMark Meserve2018-11-122-79/+85
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* mpm: i2c: Open and close i2c file descriptor on every accessAlex Williams2018-11-122-24/+48
| | | | | | This will release the i2c device when it's not in use. If MPM hangs on to the i2c devices, we won't be able to cleanly change FPGA images--The kernel hangs up the process until the refcount drops to zero.
* mpm: n3xx_bist: Add QSFP loopback to BIST testsAlex Williams2018-11-071-1/+45
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* mpm: Add basic driver for QSFP board's retimerAlex Williams2018-11-074-0/+142
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* mpm: Add convenience function to pull i2c bus from device treeAlex Williams2018-11-072-0/+37
| | | | | This function grabs the i2c character device path from the OF_NAME property. That property must be unique in the device tree!
* mpm: rh: Add MAX 10 update scriptAlex Williams2018-11-071-0/+165
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* rh: add lo distribution supportMark Meserve2018-11-053-4/+145
| | | | | | | | | - This is a combination of 5 commits. - rh: add lo distribution board gpio expander - rh: add lo distribution mpm functions - rh: add code to conditionally initialize lo distribution - rh: change empty i2c device from exception to assertion - rh: add lo distribution board control
* rh: disable lmk test outputMark Meserve2018-10-301-1/+1
| | | | - Improves spur performance
* rh: Phase DAC configuration clean-upHumberto Jimenez2018-10-301-6/+4
| | | | | | | | | | | | | | | | | | | | | - Confirmed the Phase DAC to be initialized at mid-scale. - Confirmed the Phase DAC step resolution for fine clock shifting. The clock synchronization algorithm relies on the Phase DAC to fine shift the sampling clocks on each daughterboard. Only a certain number of DAC codes are required for the actual clock adjustment, thus a different range of codes may be chosen by initializing the Phase DAC with a given value. With the selected range, one may measure the Phase DAC's linearity and step resolution, which defines how many steps are required when performing the fine shifting of the clocks. After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and 75%; it was found that the clock distribution PLL locks relatively faster when using mid-scale (2^15). By testing the Phase DAC's linearity, it was confirmed that the circuit resolution is 1.11 ps per code.
* rh: Deterministic latency optimization in JESD204BHumberto Jimenez2018-10-301-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Optimized JESD204B RX/TX links' latency. - Made JESD latency constant across supported frequencies. - Checking RX SYSREF capture in the FPGA deframer block. The JESD204B standard can be linked in such a way to produce a repeatable, deterministic delay from the framer to deframer. This is accomplished by setting up a LMFC (local multiframe clock) in both devices. The LMFCs are reset whenever a SYSREF edge is captured by the framer and deframer. Therefore, it is simple to control the LMFC rising edges in each device by implementing variable delay elements on the SYSREF pulses to the framer and deframer. Latency across the JESD204B TX/RX links should remain constant and deterministic across the supported sampling_clock_rate values. By testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with different delay values in the FPGA, one may decrease the latency and provide enough setup and hold margin for the data to be transfered through each JESD link. It was found that a different set of SYSREF delay values are required for sampling_clock_rate = 400 MSPS to match the latency of the other supported rates.
* rh: add support for rhodium devicesMark Meserve2018-10-2511-1/+2525
| | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ni.com>
* nijesdcore: add PRBS-31 testingMark Meserve2018-10-251-0/+37
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* nijesdcore: add eyescan utilityMark Meserve2018-10-253-4/+860
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* nijesdcore: add variable configuration supportMark Meserve2018-10-254-30/+50
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* mpm: tools: Added Rhodium ID to db-id utilityDerek Kozel2018-10-251-1/+3
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* mpm: e320: n3xx: Factor BIST code to common moduleMartin Braun2018-10-243-1070/+786
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* n3xx: output exception string on boot init failureMark Meserve2018-10-241-1/+1
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* mpm: Add lock_guard() functionMartin Braun2018-10-231-0/+22
| | | | | This allows sharing mutexes between C++ and Python, and uses the with statement to provide a locked-out context.
* mpm:n3xx: improve set_time_source,set_clock_sourceTrung Tran2018-10-221-50/+88
| | | | | | Add coercing behavior to set_time_source and set_clock_source to a valid sync source. Also, skip set_sync_source if device already set to the corresponding one.
* mpm: i2c: Add vector-based transfer functionAlex Williams2018-10-193-0/+41
| | | | This could lead to a less-restricted implementation for use in Python.
* mpm: Add i2c APIs for simple transfersAlex Williams2018-10-1911-0/+496
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* mg: adding skip_rfic argumentTrung Tran2018-10-182-3/+6
| | | | | | This change to add skip_rfic as an device argument. skip_rfic should be only used in ref_clock bist tests to bring down the test time.
* e320_bist: print extra output ref_clock testsTrung Tran2018-10-181-3/+6
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* n3xx_bist: add ref_clock bistTrung Tran2018-10-181-45/+107
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* mpm: identify sysfs gpios more genericallyMark Meserve2018-10-184-22/+59
| | | | | - Allow generic path names to be given for each search parameter instead of only checking the label
* N310: Clarify logging for when re-inits occurTrung Tran2018-10-161-0/+2
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* mpm: n3xx: Fix Pylint warningsMartin Braun2018-10-121-11/+12
| | | | | This commit contains whitespace and formatting changes only. No functional changes.
* mpm: dboard_manager: add more args to update_ref_clock_freqTrung Tran2018-10-123-8/+10
| | | | | | | | | | | | | | | Summary: This change will allow correct args to pass from mboard to dboards, that in turn can be useful for dboard manager. Details: In N310, the dboard manager needs the time source to be updated before calling update_ref_clock_source(), because it will trigger a reinit of the dboard, for which the time_source is essential to determine correct clock synchronizer settings. The special case is the white rabbit time source needs a different internal ref_clock_frequency for the clock synchronizer than the passed in ref_clock_freq.
* mpm: Add usrp_update_fsMartin Braun2018-10-092-0/+195
| | | | | | | This provides a new utility for MPM devices (usrp_update_fs.py), which goes through all the necessary steps to update a filesystem. Will trigger a mender update, but the tool is not specific to Mender and can be changed to use other methods in the future.
* mpm: Add __mpm_device__ as usrp_hwd module variableMartin Braun2018-10-092-0/+2
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* n3xx: e320: fixing GPSDIface sensor namesBrent Stapleton2018-09-262-2/+2
| | | | | N3xx and E320 were registering GPSDIface names as get_*_sensor instead of just the sensor name. Fixing this to now register the sensor name.
* mpm: add link_speed xport_infoTrung Tran2018-09-132-0/+22
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* tools: Fix handling of 0-valued dt-compatAlex Williams2018-09-121-1/+3
| | | | | | A value of 0 for dt-compat would cause db-init to use the rev instead. This fixes the check to be on number of args instead of the dt-compat value.
* n3xx: Get RFNoC crossbar baseport from FPGABrent Stapleton2018-09-062-2/+7
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* e320: Get RFNoC crossbar baseport from FPGABrent Stapleton2018-09-062-2/+8
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* mpm: tdc: update PDAC BIST and flatness test to use latest APIsDaniel Jepson2018-09-051-29/+35
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* mpm: reset the RPC server upon reloadBrent Stapleton2018-08-271-0/+10
| | | | | | | | | | | When reloading the Periph Manager (as when we run the image loader), we need to run the RPCServer `__init__` function in order to reset the cache of RPC methods. Otherwise, that cache keeps stale references to old functions (and prevents garbage collection). It may be possible to reset the method cache some other way, but the `_methods` attribute of RPCServer is Cython, and doesn't seem to be accessible in our Python code.
* mpm: add Git hash, version to device infoBrent Stapleton2018-08-202-1/+13
| | | | | | | | Adding MPM Git hash and version to the MPM device info. This information is currently only available through logs when MPM starts (it is the first log message in usrp_hwd.py). Adding it to the device info makes it accessible to any application which checks that, such as uhd_usrp_probe.
* mpm: mg: move init_rf_cal before JESD de/framer bringupTrung Tran2018-08-161-4/+4
| | | | This sequence is the one as described by the AD9371 user guide.
* mpm: n3xx: Improve error messages for invalid clock/time settingsMartin Braun2018-08-131-2/+4
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* mpm: n3xx: Bump max rev to G/6Martin Braun2018-08-101-1/+1
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* e320: Add all 5 temp sensors, fan sensor and rssi sensors per channelSugandha Gupta2018-08-092-21/+42
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* mpm: sys_utils: Get list of temperatures from all thermal zonesSugandha Gupta2018-08-091-4/+21
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* e320: bist: Add link_up testSugandha Gupta2018-08-061-0/+26
| | | | - Returns true if the link of sfp0 is up (1G/10G)
* adf400x: Fix adf400x driver for ref counter and charge pump modeSugandha Gupta2018-08-021-11/+19
| | | | | | | - For different ref clock frequencies, the ref_counter should change and not the n_counter. - The charge pump should be set to normal mode and tristate as that would prevent the PLL to lock.
* e320: bist: Fix ref_clock lock test implementationSugandha Gupta2018-08-021-24/+42
| | | | | | | - ref_clock_(int/ext) test was not changing adf400x driver settings for new ref clock frequency. Therefore, changed the implementation to use uhd_usrp_probe --sensor to set clock_source and get 'ref_locked' sensor value
* mpm: n3xx: clocking API changes for transitioning clock and time sourcesDaniel Jepson2018-08-024-101/+231
| | | | | | Added set_sync_source method to set both the time and clock sources without forcing a re-init twice. Modified the existing set_time_source and set_clock_source methods to call into set_sync_source.
* mpm: mg: periphs: Modify AD9361 reset function to keep it in resetMartin Braun2018-08-021-2/+9
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* e320: Update temp and fan bistSugandha Gupta2018-07-311-10/+21
| | | | | - Add mapping for 5 thermal zones for TMP464 - Update to one cooling_device as e320 has 1 fan (optional)
* e320: update sfp loopback test to load AA FPGA imageSugandha Gupta2018-07-311-19/+76
| | | | | - Load AA FPGA image before sfp bist and load default image after the test
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