aboutsummaryrefslogtreecommitdiffstats
path: root/mpm/python
Commit message (Collapse)AuthorAgeFilesLines
* mpm: Change SW/HW compat check to use last_rev_compatTrung Tran2019-05-214-18/+33
| | | | | | | Newer revisions of the E320 and N3xx motherboards use EEPROM version 3, and store a rev_compat field. The rev_compat is the last revision that this hardware is compatible with. We now use that instead of simply the revision.
* mpm: Add MB-EEPROMv3Martin Braun2019-05-211-2/+18
| | | | | | | | | | This includes a rev_compat field, which we can use to identify the last hardware revision this hardware is compatible with. Example: Say the current hardware revision is 7, but it is compatible with version 5, then we store 7 as the current rev, and 5 as the rev_compat. Software can now check the rev_compat rather than the current rev for compatibility. This makes MPM more future-proof against minor, compatible hardware changes.
* E320: Add support for rev Emichael-west2019-05-211-1/+1
| | | | | | - No driver changes required Signed-off-by: michael-west <michael.west@ettus.com>
* mpm: rpc_server: Improve error message on double-claimMartin Braun2019-02-221-2/+5
| | | | | The error message will now include the IP address of the client trying to double-claim a device.
* mpm: rhodium: Fix clock value log formattingMartin Braun2019-02-221-2/+3
| | | | | Before, the log messages would occasionally print 6 digits worth of precision for sample clock values that only require 2.
* mpm: rhodium: Fix typo in log messageMartin Braun2019-02-221-1/+1
|
* mpm: n320: Update FPGA type if QSFP board is availableMartin Braun2019-02-221-1/+9
| | | | | | The N320 has FPGA types (XQ, AQ) which cannot be derived from the mboard regs in the same way as the non-QSFP variants. We therefore bite the bullet and hardcode those.
* mpm: n320: Demote warning on absence of QSFP boardMartin Braun2019-02-221-4/+5
| | | | | The QSFP board can't be detected if support for it is not baked into the current FPGA image, so the warning on its absence may be incorrect.
* mpm: bist: DDR3 test only enumerates first blockMartin Braun2019-02-201-1/+1
|
* mpm: n3xx: bist: Auto-load the AA image for the ddr3 BISTMartin Braun2019-02-201-0/+22
| | | | | | | | | | | | | | When running $ n3xx_bist ddr3 The test will now load the AA image if the BIST fails, unless the user specifies $ n3xx_bist ddr3 -o skip_load_fpga=1 The rationale is that by default, the AA image is the only one that includes the DmaFIFO block.
* mpm: n3xx: BIST: Improve DDR3 BIST to check for DmaFIFOMartin Braun2019-02-201-6/+10
| | | | | | | The capability to run the DDR3 BIST is built into the DmaFIFO RFNoC block, which is not always available. This change performs a quick check before for its existence before retrieving the throughput values, and thus can provide a better error message in that case.
* mpm: n3xx: Remove DDR3 from standard BIST collectionMartin Braun2019-02-201-1/+1
| | | | | | | We can't guarantee that there is actually a DDR3/DRAM FIFO block on the image. So, don't run that test by default. In order to run the DDR3 bist, running `n3xx_bist ddr3` is still valid. However, it requires an image with the DRAM FIFO enabled.
* e320: add fpga_version_hash to e320 device infoSugandha Gupta2019-02-191-0/+2
| | | | | Fixes uhd_usrp_probe FPGA version githash to report the correct hash and not 'UNKNOWN'.
* mpm: n320: Properly check for the LO distribution boardMartin Braun2019-02-192-9/+23
| | | | | | | | Without this patch, the N320 code will rely on an error to occur to determine the non-existence of the N321 LO distribution board. While this works, it forces an error message where there's no error. This will first check for the existence of the board before trying to initialize it.
* N3xx: Update max rev to 7michael-west2019-02-191-2/+1
| | | | | | | Hardware revision was increased due to new firmware. No software changes are required. Signed-off-by: michael-west <michael.west@ettus.com>
* mpm: xport: add commit_xport docstringBrent Stapleton2019-02-111-1/+4
|
* n3xx: init peripherals before loading FPGATrung Tran2019-02-013-45/+64
| | | | | | | | | Issue: Current code loads FPGA too early while many essential peripherals such as net clocks are not brought up. This change will make sure those are got init before FPGA loaded. Signed-off-by: Trung Tran<trung.tran@ettus.com>
* mpm: Parameterize max UDP link allocationAlex Williams2019-01-252-1/+7
| | | | | | | Add an argument to the UDP xport_mgr to adjust the xport sorting. This enables Rhodium to use a different limit from Magnesium. Previously, the sorting method would overload a link with both of Rhodium's higher-rate streams.
* mpm: Fix up Rhodium EEPROM handling for BfrfsEEPROMAlex Williams2019-01-231-24/+3
| | | | | | Fixes Rhodium for changes introduced in b7bab6a. The constructor call for BfrfsEEPROM didn't match the signature, and Rhodium's EEPROM map referred to the wrong revision.
* rhodium: Fix some Pylint warningsMartin Braun2019-01-211-6/+4
| | | | Remove some semicolons and superfluous imports.
* mpm: n3xx: e320: Add bridge mode supportRyan Marlow2019-01-172-2/+9
|
* mpm: xportmgr_udp: Add bridge mode supportSugandha Gupta2019-01-171-18/+50
|
* mpm: ethtable: Add support for bridge mode to Ethernet dispatcherSugandha Gupta2019-01-171-21/+79
| | | | | | In bridge mode, packets may be arriving at the Ethernet device which aren't meant for this device, and thus need different routing instructions.
* mpm: net: Add bridge utilitiesSugandha Gupta2019-01-171-10/+36
|
* uhd: mpm: apply clang-format to all filesBrent Stapleton2019-01-165-87/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Applying formatting changes to all .cpp and .hpp files in the following directories: ``` find host/examples/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/tests/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/dboard/neon/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/dboard/magnesium/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/device3/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/mpmd/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/x300/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/utils/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find mpm/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file ``` Also formatted host/include/, except Cpp03 was used as a the language standard instead of Cpp11. ``` sed -i 's/ Cpp11/ Cpp03/g' .clang-format find host/include/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file ``` Formatting style was designated by the .clang-format file.
* rh: general code cleanupMark Meserve2019-01-103-8/+9
| | | | | | | | - Add default bandwidth range - Add default mash order constant - Delete MPM todos - Cleanup whitespace in MPM python code - Add docstring for is_lo_dist_present
* mpm: Add gpgga sensor function to GPSd ifaceToni Jones2019-01-031-0/+101
| | | | | | Add method to generate GPGGA sensor data in MPM devices. This needs to be constructed from TPV and SKY sensor data, and matches the GPGGA sensor functionality in gpsd_iface.cpp.
* mpm: Factor out user EEPROM code into own moduleMartin Braun2018-12-203-169/+150
| | | | | Affects Magnesium and Rhodium classes, which where duplicating this code.
* uhd/mpm: eiscat: Various changesRyan Marlow2018-12-192-28/+41
| | | | | | | | | | | | | | - correct lmk initialization parameters - adding missing parameters and consts wrt clock synchronization. - fixed default master clock rate - eiscat, ddc: update xml. - remove references to CORDIC_FREQ in ddc_eiscat - update readback reg addr in radio_eiscat - set default spp from 3992 to 3968. - updated jesd mode sequence initialization - updating eiscat_radio_ctrl_impl - add rx_codecs to property tree to display correct ADC chip. - updated issue_stream_cmd
* rh: remove polarity setting for sdclkout11Mark Meserve2018-12-121-2/+2
| | | | - output 11 is unused, a value of 0 will leave the polarity as normal
* rh: add functions to toggle lowband loMark Meserve2018-12-122-0/+20
|
* e320: Fix return value of get_fpga_typeSugandha Gupta2018-11-301-3/+3
| | | | | | Return value should be fpga image type and not sfp type, fixes a bug with uhd_image_loader while trying to update XG and AA images
* rh: Enable clock synchronization error checkingHumberto Jimenez2018-11-291-7/+3
|
* mpm: rh: Remove n321 overlayAlex Williams2018-11-271-1/+0
| | | | | | The n321 overlay is no longer needed. The devices have been added to the n320 overlay because the kernel cannot tear down multiple overlays reliably.
* n3xx: Change init() procedure to reduce configuration timeHumberto Jimenez2018-11-261-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | Previously, the init() procedure of the n3xx class passed either the user-provided or the default clock_source and time_source values to initialize the clocking configuration. When the user did not provide these parameters, the default values were assigned, overriding whatever configuration the device was previously initialized with. Therefore, a dboard reinit was forced when the currently configured state of the N3xx device did not match the default configuration (i.e. internal sources). Now, the init() procedure still provides the clock_source and time_source values; but, if the user does not provide the parameters, the previously used values are assigned (i.e. self._clock_source and/or self._time_source). By the time MPM runs this n3xx init() procedure for the first time, both self._clock_source and self._time_source have been initialized with the default internal values anyways in the _init_ref_clock_and_time() procedure. This change prevents additional, unnecessary calls to the set_sync_source() procedure, which ultimately causes a daughterboard reinitialization when either a new clock or time source is requested.
* rh: Fix update_ref_clock_freq() to update init argsHumberto Jimenez2018-11-261-0/+3
| | | | | | The update_ref_clock_freq() procedure now updates the self._init_args value of the Rhodium class daugtherboard objects in MPM to propagate the latest user-selected arguments for future reference.
* rh: fix typo in set_clk_safe_stateMark Meserve2018-11-161-1/+1
|
* mpm: add fpga githash to device infoTrung Tran2018-11-161-0/+2
|
* cmake: Update coding style to use lowercase commandsMartin Braun2018-11-149-62/+62
| | | | | | | | | | | | | | | | | Also updates our coding style file. Ancient CMake versions required upper-case commands. Later command names became case-insensitive. Now the preferred style is lower-case. Run the following shell code (with GNU compliant sed): cmake --help-command-list | grep -v "cmake version" | while read c; do echo 's/\b'"$(echo $c | tr '[:lower:]' '[:upper:]')"'\(\s*\)(/'"$c"'\1(/g' done > convert.sed \ && git ls-files -z -- bootstrap '*.cmake' '*.cmake.in' \ '*CMakeLists.txt' | xargs -0 gsed -i -f convert.sed && rm convert.sed (Make sure the backslashes don't get mangled!)
* mpm:e320: fixup gps_locked typeTrung Tran2018-11-131-1/+1
| | | | gps_locked should be a bool not int.
* mpm:gpsd_iface: handle errors from gpsdTrung Tran2018-11-131-50/+87
| | | | | | | gpsd connection is not reliable. Adding more error handling to re-connect during polling. Add control flows to get_gps_time in order to give an effect of getting the value on pps edge.
* rh: change uio access to utilize with-asMark Meserve2018-11-122-79/+85
|
* mpm: n3xx_bist: Add QSFP loopback to BIST testsAlex Williams2018-11-071-1/+45
|
* mpm: Add basic driver for QSFP board's retimerAlex Williams2018-11-074-0/+142
|
* mpm: Add convenience function to pull i2c bus from device treeAlex Williams2018-11-072-0/+37
| | | | | This function grabs the i2c character device path from the OF_NAME property. That property must be unique in the device tree!
* mpm: rh: Add MAX 10 update scriptAlex Williams2018-11-071-0/+165
|
* rh: add lo distribution supportMark Meserve2018-11-053-4/+145
| | | | | | | | | - This is a combination of 5 commits. - rh: add lo distribution board gpio expander - rh: add lo distribution mpm functions - rh: add code to conditionally initialize lo distribution - rh: change empty i2c device from exception to assertion - rh: add lo distribution board control
* rh: disable lmk test outputMark Meserve2018-10-301-1/+1
| | | | - Improves spur performance
* rh: Phase DAC configuration clean-upHumberto Jimenez2018-10-301-6/+4
| | | | | | | | | | | | | | | | | | | | | - Confirmed the Phase DAC to be initialized at mid-scale. - Confirmed the Phase DAC step resolution for fine clock shifting. The clock synchronization algorithm relies on the Phase DAC to fine shift the sampling clocks on each daughterboard. Only a certain number of DAC codes are required for the actual clock adjustment, thus a different range of codes may be chosen by initializing the Phase DAC with a given value. With the selected range, one may measure the Phase DAC's linearity and step resolution, which defines how many steps are required when performing the fine shifting of the clocks. After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and 75%; it was found that the clock distribution PLL locks relatively faster when using mid-scale (2^15). By testing the Phase DAC's linearity, it was confirmed that the circuit resolution is 1.11 ps per code.
* rh: Deterministic latency optimization in JESD204BHumberto Jimenez2018-10-301-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Optimized JESD204B RX/TX links' latency. - Made JESD latency constant across supported frequencies. - Checking RX SYSREF capture in the FPGA deframer block. The JESD204B standard can be linked in such a way to produce a repeatable, deterministic delay from the framer to deframer. This is accomplished by setting up a LMFC (local multiframe clock) in both devices. The LMFCs are reset whenever a SYSREF edge is captured by the framer and deframer. Therefore, it is simple to control the LMFC rising edges in each device by implementing variable delay elements on the SYSREF pulses to the framer and deframer. Latency across the JESD204B TX/RX links should remain constant and deterministic across the supported sampling_clock_rate values. By testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with different delay values in the FPGA, one may decrease the latency and provide enough setup and hold margin for the data to be transfered through each JESD link. It was found that a different set of SYSREF delay values are required for sampling_clock_rate = 400 MSPS to match the latency of the other supported rates.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 06:14:50 +0000