| Commit message (Collapse) | Author | Age | Files | Lines |
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Currently, AD9371 turned on most of the calibration and hard coding the turning
on process during bringup time.
This change enables users to pass in a mask field for init ARM calibration and
tracking arm calibration at the time creating USRP device reference.
This mask field can be passed through device arguments of:
1/ init_cals : for init ARM calibration masks. This is defined in AD9371 UG-992
table 65. Default to 0x4DFF
2/ tracking_cals : for tracking calibration masks. This is defined in AD9371
UG-992 table 66. Default to 0xC3
Example of pasing in init calibration and tracking calibration mask
usrp_application --args "init_cals=0x4f, tracking_cals=0xC3"
NOTE: UHD currently expect user to input the correct init_cals and
tracking_cals. There's no mechanism to check if init mask and tracking mask are
valid. For example if the init mask field not mask 0x4f, the AD9371 will failed
to setup.
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Note: The AD9371 lock sensors are only stubbed out for now.
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SPI interfaces and -lock, user EEPROM, radio regs, CPLD, dboard clock
control and GPIO expander can be initialized in Magnesium.__init__().
This shaves a little time off of the actual init() call and allows for
earlier failures.
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- Removed superfluous code
- Fixed most PyLint warnings
- Reordered methods to match call order
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Log prefixes weren't properly being set.
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This increases init speed by replacing worst-case sleeps with polls.
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- Moved AD9371 API generation around
- Fixed some PyLint warnings
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The Magnesium daughterboards have GPIO port expanders, but both have the
same udev label. In order to specify which port expander to use, we pass
in the parent udev I2c device.
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- Based on feedback from ADI, updated SYSREF sequencing for
meeting deterministic latency requirements.
- Changed majority of register addresses in nijesdcore.py to
constants.
- Corrected write data to SYSREF_CAPTURE_CONTROL to produce
the correct SYSREF toggle rate inside the FPGA.
Signed-off-by: djepson1 <daniel.jepson@ni.com>
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Signed-off-by: djepson1 <daniel.jepson@ni.com>
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Signed-off-by: djepson1 <daniel.jepson@ni.com>
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Signed-off-by: djepson1 <daniel.jepson@ni.com>
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Signed-off-by: djepson1 <daniel.jepson@ni.com>
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- add clock shifting
- add DAC support
- modify __init__ calls for cleanup
Signed-off-by: djepson1 <daniel.jepson@ni.com>
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- Make DB probe-able
- Add RPC client
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Also cleaned up some cruft.
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indexing to numbers
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- EISCAT is now Python only with the exception of the definition of the
SPI ifaces
- Magnesium uses a Python-generated SPI iface
- Removed SPI lock from EISCAT dboard
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Note: This requires a new FPGA image, or Mykonos simply won't reset.
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Also currently hardcodes some settings.
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- Send user defined data in ping
- Improve rpc_shell, add mpm_debug.py, fix tracebacks in multiprocessing
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