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- Returns true if the link of sfp0 is up (1G/10G)
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- ref_clock_(int/ext) test was not changing adf400x driver settings
for new ref clock frequency. Therefore, changed the implementation
to use uhd_usrp_probe --sensor to set clock_source and get
'ref_locked' sensor value
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- Add mapping for 5 thermal zones for TMP464
- Update to one cooling_device as e320 has 1 fan (optional)
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- Load AA FPGA image before sfp bist and load default image
after the test
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- E320 will support only 3.3 V for the front panel GPIO
- Remove other voltage options
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