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* rh: initialize switchesMark Meserve2018-11-071-3/+10
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* docs: x300: Add section on motherboard clockingMartin Braun2018-11-071-0/+50
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* x300: Remove 120 MHz optionMartin Braun2018-11-072-3/+1
| | | | | None of our FPGA images support a 120 MHz master clock rate, so the UHD code should match that.
* rh: adjust tx lo gain tableMark Meserve2018-11-052-7/+12
| | | | - Improves performance for frequencies greater than 3.5 GHz
* rh: add lo distribution supportMark Meserve2018-11-054-0/+161
| | | | | | | | | - This is a combination of 5 commits. - rh: add lo distribution board gpio expander - rh: add lo distribution mpm functions - rh: add code to conditionally initialize lo distribution - rh: change empty i2c device from exception to assertion - rh: add lo distribution board control
* rh: fix handling of spur_dodging argMark Meserve2018-11-013-7/+30
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* uhd: Changes to traffic counter register namesCiro Nishiguchi2018-10-312-78/+62
| | | | | | This makes the noc traffic counter register actually reflect the registers in the FPGA. The FPGA register names were changed prior to merging to master, and the ready count registers were removed.
* tests: device3_test: add graph impl testTrung Tran2018-10-317-59/+295
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* debian: Update control files for .deb filesMartin Braun2018-10-294-21/+29
| | | | | | | | | - Better alignement with public Debian files. - Move to a different package name: libuhd003.so -> libuhd3.13.0.so This allows to install multiple packages in parallel for better ABI compatibility by third-party dependees. The new package replaces the old one. - Remove .shlibs file
* cmake: Change SOVERSION and VERSION for the library filesMartin Braun2018-10-292-2/+9
| | | | | | The SOVERSION will now match the ABI string, and the VERSION matches the full UHD version. This will allow easier parallel installation of multiple versions of UHD.
* cores:rx_frontend_core_3000: fix real modeGwenhael Goavec-Merou2018-10-291-0/+2
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* python: Add missing constructors of time_spec_tPiotr Krysik2018-10-251-0/+3
| | | | | | Currently Python interface of time_spec_t exposes only constructor with 'double' parameter. Other constructors are also important as they provide higher precision. This change adds them to the Python API.
* rh: add support for rhodium devicesMark Meserve2018-10-2515-3/+3622
| | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ni.com>
* Test: Add unit test for eeprom_utilsmichael-west2018-10-254-2/+63
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* X300: Prevent duplicate MAC and IP addresses from being programmed in MBMichael West2018-10-252-2/+104
| | | | EEPROM
* X300: Add recovery for duplicate IP addresses in EEPROMMichael West2018-10-252-19/+13
| | | | | - Limit initialization to ZPU communication if recover_mb_eeprom=1 is set in device args.
* block_ctrl_base: add UHD_SAFE_CALL to destructorTrung Tran2018-10-241-13/+15
| | | | | This will stop the exception throw during destructor of E310 where new FPGA image(idle image) is load.
* cmake: Bump CMake minimum version to 2.8.12Martin Braun2018-10-241-2/+2
| | | | | | This enables some interesting features we can now use in UHD, such as: - target_compile_options - add_compile_options
* UHD: Fix RX streamer SOB and EOB handlingMichael West2018-10-241-2/+9
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* multi_usrp: Improve documentation for set_{time,clock,sync}_sourceMartin Braun2018-10-221-14/+95
| | | | | - Added note on bad-value-handling (throws uhd::value_error) - Added notes on what happens on re-init
* docs: n3xx: Improve sections on clock/time referencesMartin Braun2018-10-221-9/+22
| | | | | | - Added more detail on how to use White Rabbit - Highlight the options with external clock source (with or without external time source)
* uhd: Add dual measurements to benchmark_streamerCiro Nishiguchi2018-10-181-113/+314
| | | | | Add options to run benchmark_streamer with multiple streamers running concurrently on separate threads.
* twinrx: revise adf5356 frac2 register calculationMark Meserve2018-10-171-1/+1
| | | | | - If FRAC2 isn't exactly FRAC1 at certain frequencies, drifting spurs can be seen in the spectrum
* B200: Restore asynchronous reset of AD936x.michael-west2018-10-172-4/+15
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* e320: Added E320 docs page, reg map updatedSugandha Gupta2018-10-172-0/+707
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* lmx2592: remove initial scratch register readbackMark Meserve2018-10-171-24/+0
| | | | | - This is the only read operation in the driver, so removing it simplifies the driver's requirements significantly.
* lmx2592: add spur dodgingMark Meserve2018-10-172-23/+330
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* lib: ad9361: De-boostify AD9361 driverMartin Braun2018-10-172-106/+195
| | | | No functional or API changes.
* docs: Fix N210 MIMO Phase Alignment commandBrent Stapleton2018-10-121-1/+1
| | | | | | | The synchronization source for the N210 MIMO phase alignment needs to be set to anything other than 'pps' or 'auto' (which is actually 'pps'). 'default' skips the call to `set_time_unknown_pps`, which is the proper way to synchronize in this sitation.
* utils: fix bmark_rate MIMO synchronizationBrent Stapleton2018-10-121-9/+10
| | | | | | | | | | Fix USRP2 MIMO synchronization in benchmark_rate. When synchronizing N2XXs connected with a MIMO cable, only the master's time needs to be set; the slave will be synchronized automatically. Currently, calling set_time_unknown_pps will attempt to synchronize the slave on the next PPS, which can cause problems since the MIMO cable doesn't propogate a PPS signal.
* uhd: Improve documentation for the UHD exception typesMartin Braun2018-10-121-0/+51
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* multi_usrp: Add sync_source APIMartin Braun2018-10-112-6/+211
| | | | | | | | | | The sync_source API is an atomic setter for all sync-related settings. If supported by the underlying USRP, it can be faster to call set_sync_source() rather than sequentially calling set_clock_source() and set_time_source(). If the underlying device does not support the sync_source API, it will fall back to the set_clock_source() and set_time_source() APIs, making this change backward-compatiple.
* uhd: Add benchmark_streamer exampleCiro Nishiguchi2018-10-112-0/+498
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* uhd: Add traffic counter to null source sinkCiro Nishiguchi2018-10-112-0/+100
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* mpmd: Increase rpcc timeout when calling set_time_source()Trung Tran2018-10-111-0/+2
| | | | | | | set_time_source() for N310 and N300 can take longer than the default RPC client timeout of 2 seconds due to dboard initialization. We need increase this timeout, by using the init timeout value which is 2 minutes.
* docs: Added TwinRX pageDerek Kozel2018-10-095-0/+91
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* uhd: Fix rounding in ddc/duc rate calculationCiro Nishiguchi2018-10-052-2/+2
| | | | | | | | The DDC and DUC convert the requested rate to an integer before selecting a decimated / interpolated rate. This causes the selection to select a lower rate than requested in some corner cases. The effect is more pronounced when the input rate of the DDC or the output rate of the DUC is very small.
* mg: fixup set_rx_antennaTrung Tran2018-10-041-1/+1
| | | | | | After going to 2 radios configuration (FPGA), the channnel value is passed into this set_rx_antenna now have value either 0 or 1. We want the mapping of {radio_channel:cpld_channel} = {0:CHAN1} or {1:CHAN2}.
* multi_usrp: move definition of constantsAndrew Lynch2018-10-042-2/+4
| | | | ALL_MBOARDS and ALL_CHANS will be exported on GCC and MSVC
* uhd: reconcile time_spec operators with boost conceptsMark Meserve2018-09-282-18/+14
| | | | | | - Removes operator+ which was ambiguously defined in some cases - Adds additive concept for time_spec_t and double operators - Remove unnecessary ctime header
* rfnoc: install the DMA FIFO block headerMarcus Müller2018-09-261-0/+1
| | | | Reported-by: Brian Padalino <bpadalino@gmail.com>
* e320: devtest: Reduce sample rate for 1G devtestSugandha Gupta2018-09-261-1/+1
| | | | | | The E320 default master clock rate is 16MHz, therefore we need to reduce the 2 channel receive rate to 8MHz in order to be able to meet the requested rate.
* cores: Update rx_frontend_gen3.v controls for 1/4-rate mixerMartin Braun2018-09-252-8/+12
| | | | | | | This tracks the changes on rx_frontend_gen3.v, which was updated to use a quarter-rate downconverter instead of a generic CORDIC. The X3x0 FPGA compat number is incremented as the rx_frontend is part of the device architecture rather than an RFNoC block.
* e320: Fix master_clock_rate settingSugandha Gupta2018-09-241-0/+4
| | | | | | The master clock rate was getting overwritten while running the codec loopback self test. So now we save the current rate before running the test and then reapply it.
* e320: Add R&D testing procedureSugandha Gupta2018-09-241-12/+120
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* examples: add rfnoc_radio_loopbackTrung Tran2018-09-142-0/+214
| | | | This example will allow an RF->RF loopback using RFNoC devices.
* uhd: rfnoc: add async message handlerTrung Tran2018-09-147-9/+421
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* radio_ctrl: add disable time stampTrung Tran2018-09-143-0/+13
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* devtest: n3x0: Enable rx_samples_to_file testSugandha Gupta2018-09-141-1/+1
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* mg: clipping frequencyTrung Tran2018-09-142-4/+7
| | | | | Clipping requested frequency to acceptable ranges in Magnesium TX/RX set frequency functions.
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