| Commit message (Collapse) | Author | Age | Files | Lines |
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- We added additional microcode to configure DCI matching,config rate,etc
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- The value was originally empirically determined based on self-cal
results. After the fix for uncalibrated IDELAY, the self-cal offset
data was no longer correct.
- The new delay through the ADC ensures that the self-cal nominally
pick the halfway tap of 16
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- Everytime the LMK is configured, we do the following:
- Reset all LMK regs
- Wait for LMK lock
- Reset radio_clk PLL in FPGA
- Wait for FPGA PLL to lock
- Assert radio_rst which resets downstream radio logic
- This address the intermittent self-cal failures due to uncalibrated IDELAY taps
- Bumped FPGA compat to 12
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- This changed with the ADS62P44 -> ADS62P48 design change
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Conflicts:
host/include/uhd/transport/nirio/nirio_driver_iface.h
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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All currently available e3xx daugherboards are equivalent from
a UHD perspective, so make them consistently show up as "E3XX".
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- New device arg "ext_adc_self_test" triggers the test
- ext_adc_self_test=<time> runs the test for "time" seconds
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- product code, revision and revision compat errors are now exceptions
- Added recover_mb_eeprom arg to recover from a corrupt/uninitialized EEPROM
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- Added new field "revision_compat" to mb_eeprom
- Enforce a revision_compat of 7
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- Added new PCIe and MB PIDs for new boards
- Added an error if MB PID is invalid
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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* Single class for loading firmware/FPGA images onto devices instead of multiple utilities
* Loading functions are registered for each device, corresponding to their --args="type=foo" name
* Deprecation warnings added to all product-specific image loading utilities
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- X300 Rev7 images
- B200 updated firmware (V8)
- OctoClock
- E300 (idle image)
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- B2x0: FW compat number (goes with previous firmware update)
- X3x0: Max HW rev number
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Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
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- Updated fpga-src
- Updated version strings
- Updated images package
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This was originally limited because it performed poor,
however, with refactoring that has been done since release,
this now gives better performance.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This commit will have UHD load the idle fpga image on
destruction of e300_impl.
Note: This requires usrp_e310_idle_fpga.bit to be present
in the UHD images directory.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- If the self-cal fails, UHD waits for 2 sec for the ADC temp
to stabilize and retries the self-cal
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- Characterized over process and temperature
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Fixes issue #828 "B200: Tx quadrature calibration regression in master"
Following commit added new gain table settings to reflect updated values
from ADI. Gain indices used by Tx Quad Cal were not matched to
accommodate the new tables.
2b06c38 "b2xx: dc offset and iq imbalance correction control"
Requirement for Tx Quad Cal is for TIA gain and analog LPF gain to be
set at 0 dB, or 0x20 in the gain table. Final effect is a dramatic
decrease in Tx DC offset and quadrature image.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Patch fixes a portion of #807
"B210: severe distortion on In-phase data for some gain settings"
ADI recommends that the "Prevent Pos Loop Gain" setting be enabled to
prevent the Rx quadrature tracking loop from becoming unstable at low
power levels. ADI Linux kernel driver also reflects this setting.
We do not follow the ADI recommendation. Adjust accordingly.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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This patch resolves issue #823
"B200: Receive RF DC calibration makes calibration worse below 34 dB"
According to ADI reference documents, enabling any of the 3 LNA's in the
receive path causes a 180 degree phase shift. Correspondingly, we invert
the LNA bypass path (gain indices below 34 dB) to match. Testing,
however, reveals that one of these statements or the polarity inversion
setting itself is false. Disabling the switch results in expected
behavior and proper phase alignment.
Overall effect is up to 60 dB of DC offset suppression ahead of the Rx
analog LPF. This reduces the problematic dependency on active baseband
tracking and may resolves multiple tracking stability issues.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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