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Updated to output current year. Changed capitalization and wording to
be consistent with exisiting code.
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This adds a new option to the "AXI-Stream Data" (axis_data) FPGA
interface type. The new option, "sideband_at_end", can be added to the
output port of a block's YAML description to control whether the
sideband information should be sampled at the end (sideband_at_end: 1)
or the beginning (sideband_at_end: 0) of the AXI-Stream packet.
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This replaces chdr_word_t, which was a statically defined 64-bit data
type, with a paramaterizable data type that matches the defined CHDR_W.
Code that formerly referenced the chdr_word_t data type can now define
the data type for their desired CHDR_W and ITEM_W as follows:
// Define the CHDR word and item/sample data types
typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t;
ITEM_W is optional when defining chdr_word_t if items are not
needed. Static methods in the ChdrData class also provide the ability to
convert between CHDR words and data items. For example:
// Convert CHDR data buffer to a buffer of samples
samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
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- Fix mako paths to run from anywhere
- Correct code errors and clean up generated code
- Add support for port parameters
- Add support for axis_data interface
- Fix NoC shell reset handling
- Replace Python functions with Verilog $clog2
- Allow input and output to share port name
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This commit removes all files and parts of files that are used by
proto-RFNoC only.
uhd: Fix include CMakeLists.txt, add missing files
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This is an initial generator for eRFNoC block.
The script generates the top level block, the shell module, a testbench, and a
Makefile as well as a Makefile.srcs.
To build a block from a yml file one has to invoke
python -c <config> -d <destination folder>
destination folder should be an in tree module folder located in
uhd-fpga/usrp3/lib/erfnoc/blocks
The build tool supports all interface types for control as well as data.
For each interface type there are three templates to generate the variable
block in the top level block and the shell
* declare the wires
* connect the wires
* instantiate the modules
The first two are used in the shell module as well as in the top level block.
The last is for the shell only.
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