uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	utils: Set rfnoc_create_verilog.py as executable	Wade Fife	2020-10-09	1	-0/+0
*	utils: Update mako to propagate parameters	Wade Fife	2020-05-11	2	-13/+27
*	Remove remaining Python 2 references	Martin Braun	2020-05-07	1	-1/+1
*	utils: Remove trailing white space from mako templates	Wade Fife	2020-04-30	2	-4/+4
*	utils: Fix typo in testbench mako template	Wade Fife	2020-04-30	1	-1/+1
*	utils: Update copyright generated by blocktool	Wade Fife	2020-04-23	5	-5/+5
*	utils: Add sideband_at_end support to Mako template	Wade Fife	2020-04-21	3	-15/+22
*	utils: Fix comment in axis_data template	Wade Fife	2020-04-14	1	-1/+1
*	examples: Update gain block testbench to use samples	Wade Fife	2020-03-09	1	-1/+1
*	sim: Parameterize chdr_word_t data type	Wade Fife	2020-03-09	1	-1/+6
*	fixup! utils: blocktool: Fix blocktool	Wade Fife	2020-02-06	2	-5/+5
*	utils: blocktool: Fix blocktool	Wade Fife	2019-11-26	25	-585/+1402
*	Remove proto-RFNoC files	Martin Braun	2019-11-26	2	-11/+11
*	rfnoc: add eRFNoC block builder to generate boiler plate Verilog	Lars Amsel	2019-11-26	18	-0/+1069