aboutsummaryrefslogtreecommitdiffstats
path: root/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py
Commit message (Collapse)AuthorAgeFilesLines
* utils: blocktool: Fix blocktoolWade Fife2019-11-261-3/+5
| | | | | | | | | | - Fix mako paths to run from anywhere - Correct code errors and clean up generated code - Add support for port parameters - Add support for axis_data interface - Fix NoC shell reset handling - Replace Python functions with Verilog $clog2 - Allow input and output to share port name
* rfnoc: add eRFNoC block builder to generate boiler plate VerilogLars Amsel2019-11-261-0/+131
This is an initial generator for eRFNoC block. The script generates the top level block, the shell module, a testbench, and a Makefile as well as a Makefile.srcs. To build a block from a yml file one has to invoke python -c <config> -d <destination folder> destination folder should be an in tree module folder located in uhd-fpga/usrp3/lib/erfnoc/blocks The build tool supports all interface types for control as well as data. For each interface type there are three templates to generate the variable block in the top level block and the shell * declare the wires * connect the wires * instantiate the modules The first two are used in the shell module as well as in the top level block. The last is for the shell only.