| Commit message (Collapse) | Author | Age | Files | Lines |
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Issues #649 & #691
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* Point to usrp2_card_burner_gui.py instead of usrp2_card_burner.py
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b200: Bugfix#692: b200_find now returns an empty device vector when hint...
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contains addr0/resource0/etc style keys.
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Adds more methods: {set,get}_normalized_{tx,rx}_gain() which
allow changing and reading back the gain within [0, 1].
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Conflicts:
host/examples/rx_samples_to_file.cpp
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Conflicts:
fpga-src
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Resolved Conflicts:
host/docs/usrp_e3x0.dox
host/include/uhd/utils/paths.hpp
host/lib/transport/nirio/nifpga_lvbitx.cpp
host/lib/usrp/b200/b200_impl.cpp
host/lib/utils/paths.cpp
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- Converter ID symbols are exported
- to_string() function for lighter feedback
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Conflicts:
host/docs/usrp_e3x0.dox
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This allows to read a relative temperature from an AD9361 device.
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Conflicts:
host/include/uhd/types/direction.hpp
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Conflicts:
host/include/uhd/types/CMakeLists.txt
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* Added CMake toolchain file, compatible with different versions
* No dependency on MinGW runtime, all statically linked
* Misc coding tweaks to allow MinGW to compile
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Conflicts:
host/examples/rx_samples_to_file.cpp
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- Bugfix for #638
- get_ref_locked will check lock status one last time before giving up
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Our VRT routines have the option to switch, on the fly, between
VRLP and CHDR. This adds new CHDR-specific (un-)packers, which
can only work with CHDR.
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- Deleted images.*, moved functionality to paths.*
- Applies for all devices that check FPGA or FW compat numbers
- Adds generic utility search tool
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Conflicts:
host/lib/usrp/b200/b200_impl.hpp
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When no master_clock_rate is defined, the B200 driver will now
select a suitable clock rate automatically based on the selected
sampling rate.
The selected tick rate is a multiple of the LCM of tx and rx rates.
Auto-setting is done every time a streamer is generated or the sampling
rate is configured.
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- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
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