| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | Changed analog delay on DAC reference and radio clocks from 1075ps to 900ps | michael-west | 2014-08-18 | 1 | -4/+4 | |
| | | | | ||||||
| | | * | - Fixes for channel alignment | michael-west | 2014-08-18 | 5 | -56/+42 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added analog delay for radio clock - Added analog delay for DAC reference clocks - Removed resetting of clock control - Removed setting of reference clock and PPS to external sources during initialization - Fixes for set_time_unknown_pps - Removed wait for PPS edge after setting time from GPSDO - Changed set_time_unknonw_pps to time out based on system time rather than device VITA time | |||||
| | * | | Merge branch 'maint' | Martin Braun | 2014-08-18 | 4 | -4/+4 | |
| | |\| | ||||||
| | | * | Restoring compatibility with CMake 2.6 | Nicholas Corgan | 2014-08-14 | 4 | -4/+4 | |
| | | | | | | | | | | | | | | | | * The UNSET command didn't exist back then, but using SET with no value does the same thing * CMake 2.6 doesn't like nested parantheses in IF statements, so tweak IF/ELSE statements | |||||
| * | | | ad9361: Fixed MSVC build issues | Ashish Chaudhari | 2014-08-13 | 2 | -2034/+2039 | |
| | | | | ||||||
| * | | | ad9361: Fixed debug messages with UHD_LOGs | Ashish Chaudhari | 2014-08-13 | 1 | -19/+15 | |
| | | | | ||||||
| * | | | ad9361: Fixed TX direction bug in ad9361_ctrl | Ashish Chaudhari | 2014-08-13 | 1 | -1/+1 | |
| | | | | ||||||
| * | | | ad9361: Added synchronization to IO and device classes | Ashish Chaudhari | 2014-08-13 | 3 | -20/+36 | |
| | | | | ||||||
| * | | | ad9361: Cleaned up constants and macros | Ashish Chaudhari | 2014-08-13 | 4 | -84/+67 | |
| | | | | ||||||
| * | | | ad9361: Cleaned up errors and debug messages | Ashish Chaudhari | 2014-08-12 | 1 | -45/+46 | |
| | | | | ||||||
| * | | | ad9361: Converted stdint types to boost types | Ashish Chaudhari | 2014-08-12 | 7 | -136/+133 | |
| | | | | ||||||
| * | | | ad9361: Renamed ad9361_impl.c to ad9361_device.cpp | Ashish Chaudhari | 2014-08-12 | 2 | -6/+1 | |
| | | | | ||||||
| * | | | b200, ad9361: Cleanup up AD9361 driver | Ashish Chaudhari | 2014-08-12 | 13 | -1553/+1122 | |
| | | | | | | | | | | | | | | | | - Removed transaction interface - Made the driver a C++ class | |||||
| * | | | b200: Removed all AD9361 related firmware | Ashish Chaudhari | 2014-08-12 | 3 | -85/+1 | |
| |/ / | | | | | | | | | | | | | - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6 | |||||
| * | | Merge branch 'master' into ashish/cat_refactor_master | Ashish Chaudhari | 2014-08-05 | 4 | -11/+35 | |
| |\ \ | ||||||
| | * | | Merge branch 'maint' | Martin Braun | 2014-07-31 | 4 | -11/+35 | |
| | |\| | | | | | | | | | | | | | Conflicts: host/utils/usrp_burn_mb_eeprom.cpp | |||||
| | | * | Merge branch 'maint' into uhd/bug492 | michael-west | 2014-07-30 | 7 | -49/+167 | |
| | | |\ | | | | | | | | | | | | | | | | | Conflicts: host/lib/usrp/b200/b200_impl.cpp | |||||
| | | | * | tx fe corrections: fixing mixed tabs / spaces, other horrible whitespace cruft | Ben Hilburn | 2014-07-25 | 2 | -14/+11 | |
| | | | | | ||||||
| | | | * | Merge 'maint' into x300/bug513 | Ben Hilburn | 2014-07-25 | 2 | -3/+4 | |
| | | | |\ | ||||||
| | | | * | | X300: Added UHD support for TX FE | Ian Buckley | 2014-07-18 | 2 | -1/+14 | |
| | | | | | | ||||||
| | | * | | | Fix for BUG #492: UHD: set_time_unknown_pps() fails with GPSDO installed | michael-west | 2014-06-25 | 3 | -3/+17 | |
| | | | | | | | | | | | | | | | | | | | | | - Added polling for PPS time change after setting time from GPSDO. | |||||
| * | | | | | b200: Added variable rate SPI core for AD9361 and ADF4001 | Ashish Chaudhari | 2014-08-01 | 8 | -8/+159 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Added b200_local_spi core that adjusts the divider when talking to the two chips - AD9361 rate is 1MHz and ADF4001 rate is 10kHz | |||||
| * | | | | | b200: Moved AD9361 driver to host | Ashish Chaudhari | 2014-08-01 | 18 | -131/+2872 | |
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow | |||||
| * | | / | OctoClock firmware upgrade, added host driver | Nicholas Corgan | 2014-07-23 | 18 | -27/+1263 | |
| | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | * OctoClock can communicate with UHD over Ethernet * Can read NMEA strings from GPSDO and send to host * Added multi_usrp_clock class for clock devices * uhd::device can now filter to return only USRP devices or clock devices * New OctoClock bootloader can accept firmware download over Ethernet * Added octoclock_burn_eeprom,octoclock_firmware_burner utilities * Added test_clock_synch example to show clock API | |||||
| * | | | Commented out warning if X300 reference clock fails to lock within 1 second ↵ | michael-west | 2014-07-22 | 1 | -2/+3 | |
| | | | | | | | | | | | | | during initialization. Sometimes it takes longer and that is OK. | |||||
| * | | | Fix for BUG #517: B200: Regression of power level on RX | michael-west | 2014-07-22 | 1 | -1/+1 | |
| | |/ |/| | | | | | - Fixed scalar for RX DSP core | |||||
| * | | Updated copyright year. | michael-west | 2014-07-17 | 1 | -1/+1 | |
| | | | ||||||
| * | | Fix for BUG #469 | michael-west | 2014-07-17 | 1 | -0/+2 | |
| | | | | | | | | | - Added mutex for write_uart() | |||||
| * | | - Changed variables from uint8_t to uint32_t so parsing of hex strings would ↵ | michael-west | 2014-07-17 | 1 | -3/+3 | |
| | | | | | | | | | work properly. | |||||
| * | | Addressing comments from review. | michael-west | 2014-07-17 | 2 | -15/+21 | |
| | | | | | | | | | | | | | - Corrected types of some variables to be boost types. - Removed debugging code accidentally left in. - Changed some compiled out error messages to log messages. | |||||
| * | | Fix for BUG #469: Bad/Empty GPS NMEA strings returned when the queries are ↵ | michael-west | 2014-07-17 | 2 | -20/+108 | |
| | | | | | | | | | | | | | | | | | | | made in a random wait iterative fashion Fix for BUG #460: X300: GPGGA sensor most often empty, while RMC is usually OK - Added checksum verification of NMEA strings - Improved handling of short or malformed strings - Fixed GPSDO data synchronization between X300 firmware and host | |||||
| * | | Merge branch 'origin/b200/bug516' into maint | Ben Hilburn | 2014-07-17 | 1 | -4/+4 | |
| |\ \ | | | | | | | | | | Fixing B200 clock rate float compare. | |||||
| | * | | BUG #516: B210: Fails to Run with 30.72 MHz Clock | michael-west | 2014-07-10 | 1 | -1/+1 | |
| | | | | | | | | | | | | | - Addressed feedback from review. | |||||
| | * | | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock | michael-west | 2014-06-18 | 1 | -3/+3 | |
| | | | | | | | | | | | | | - Corrected clock rate checks for B2x0 | |||||
| | * | | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock | michael-west | 2014-06-18 | 1 | -3/+3 | |
| | |/ | | | | | | | - Corrected clock rate checks for B2x0 | |||||
| * | | Merge branch 'origin/ashish/rx_pcie_overflows' into maint | Ben Hilburn | 2014-07-17 | 2 | -3/+7 | |
| |\ \ | ||||||
| | * | | x300: Bugfix for overflows on PCIe at 200MS/s | Ashish Chaudhari | 2014-06-27 | 2 | -3/+7 | |
| | |/ | ||||||
| * | | Merge branch 'origin/b200/bug512' into maint | Ben Hilburn | 2014-07-17 | 1 | -9/+15 | |
| |\ \ | | | | | | | | | | B200 now creates internal PPS. Depends on FPGA change. | |||||
| | * | | Enhancement #512: B210: Need an Internal PPS | michael-west | 2014-06-13 | 1 | -9/+15 | |
| | | | | | | | | | | | | | - Added support for internal PPS selection (set as default) | |||||
| * | | | Fix for BUG #527: N200: 50 Msps results in two tones | michael-west | 2014-07-01 | 1 | -1/+2 | |
| | |/ |/| | | | | | - Adjusted check to enable first half-band filter only if the rate is decimated enough between the CIC and other half-band filter | |||||
| * | | Merge branch 'origin/b200/bug500' into maint - Fixing B200 phase alignment issue | Ben Hilburn | 2014-06-16 | 3 | -3/+9 | |
| |\ \ | ||||||
| | * | | - Changed XOR to OR for REG_DSP_RX_MUX flags. | michael-west | 2014-06-12 | 1 | -3/+3 | |
| | | | | ||||||
| | * | | Fix for BUG #500: B210: RX channels are not phase aligned | michael-west | 2014-06-06 | 3 | -3/+9 | |
| | | | | | | | | | | | | | - Adding UHD side code to invert second RX channel | |||||
| * | | | Fix issue with "item32" registered size, Bug 466. | Ben Hilburn | 2014-06-13 | 1 | -0/+3 | |
| |\ \ \ | |_|/ |/| | | ||||||
| | * | | UHD: Addressing Bug 466, as per Balint. | Ben Hilburn | 2014-05-22 | 1 | -0/+3 | |
| | | | | ||||||
| * | | | Do not set the mfloat-soft flag during the test for arm_neon.h. | Philip Balister | 2014-06-03 | 1 | -7/+0 | |
| |/ / | | | | | | | | | | | | | Use the flags passed in from the toolchain. If this test runs on a hard-float system, bad things happen. Signed-off-by: Philip Balister <philip@opensdr.com> | |||||
| * / | Lots of bit-specific type work to fix compilation on older OSes. | Ben Hilburn | 2014-05-21 | 4 | -15/+15 | |
| |/ | ||||||
| * | x300: adding include to fix builds on older systems | Ben Hilburn | 2014-05-20 | 1 | -0/+1 | |
| | | ||||||
| * | Fixing Bug #473 - Autoselection of VCO Frequency in DBSRX2 | Ben Hilburn | 2014-05-20 | 1 | -6/+8 | |
| |\ | ||||||
| | * | Fixed whitespace and added comment. | michael-west | 2014-05-20 | 1 | -5/+6 | |
| | | | ||||||
 |
index : uhd | |
| Ettus' UHD Repository |
| aboutsummaryrefslogtreecommitdiffstats |