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* dsp: clear register now overlaps with numchan register.Josh Blum2012-04-091-4/+2
| | | | This fixes the bug of unwanted clearing when setting format.
* usrp: fix set_clock_config typo for external and mimo clock refJosh Blum2012-04-061-2/+2
| | | | | | This is a typo in the set_clock_config implementation. However, the enum values are the same, so this would not cause a bug. Fixed although set_clock_config is a deprecated interface.
* usrp1: stop threads in deconstructorJosh Blum2012-03-293-4/+10
| | | | | | | | | | | | | | | Its important to stop the threads before we let the other smart point objects naturally deconstruct to avoid thread-based race conditions. The attempt to deconstruct the tree and soft time ctrl had a bug because the tree had references in subtrees within the dboard manager class. Rather than continue to fix this method and deconstruct the tree to free up soft time ctrl, it seems simpler to just stop the thread in soft time ctrl, and then let it naturally deconstruct later by ref count.
* dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHzJosh Blum2012-03-261-1/+8
| | | | | This fixes the lockup/clocking condition when the following hw combo is used: USRP1 r4.5 + DBSRX + another i2c board
* usrp2: possible fix for invalid broadcast repliesJosh Blum2012-03-261-3/+17
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* usrp: fix for rx_frontend_core_200 dc offsetJosh Blum2012-03-231-3/+4
| | | | | Mask off upper bits when setting a constant offset (I and Q regs). The sign bits (if negative) can flow off into the flags field.
* usrp: fix typo for user setting regJosh Blum2012-03-211-1/+1
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* uhd: add calls to query an ABI compat stringJosh Blum2012-03-211-1/+5
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* Disabling the SBX mixer and baseband amp causes griefJason Abele2012-03-161-1/+1
| | | | | Some ADA4927 / AD5380 combinations do not appreciate being disabled, so lets not disable them
* B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the ↵Nick Foster2012-03-161-2/+2
| | | | "stuffing zeroes" problem and improves transport reliability.
* usrp: fix from "rev iq correction"Josh Blum2012-03-163-6/+6
| | | | Must zero out the default IQ correction to have zero effect by default.
* n2x0: adjustment for phase delay over mimo cableJosh Blum2012-03-141-1/+1
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* uhd: make atlbase options for msvc buildJosh Blum2012-03-142-4/+16
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* uhd: rev iq correction numbers formatJosh Blum2012-03-143-47/+10
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* usrp: fix wildcard set for time/clock sourceJosh Blum2012-03-121-2/+2
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* uhd: added fullscale option stream argJosh Blum2012-03-112-0/+4
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* Make DBSRX* set default bandwidth based on codec rateJason Abele2012-03-112-2/+7
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* Fix RSSI measurementJason Abele2012-03-112-18/+4
| | | | | | Improve incorrect calculation in XCVR Remove RFX rssi sensor due to limited dynamic range giving strange results
* usrp1: fix for cordic init, cant do it that way on txJosh Blum2012-02-291-3/+0
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* uhd: fix sc16 to sc8 conversion tableJosh Blum2012-02-291-12/+12
| | | | | | | 1) this was registered as the sc8 to sc16 converter, probably messed that up as well 2) the cast to index was wrong, now unit test passes
* usrp2: device locking tweaksJosh Blum2012-02-291-9/+6
| | | | | | | 1) use bottom bit for force lock condition, that way we never check the time after proper shutdown 2) dont allow lock condition under fpga compat mismatch
* usrp: reset cordics on init after tick rate updateJosh Blum2012-02-284-0/+33
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* uhd: fixed some compile warnings for msvcJosh Blum2012-02-283-3/+3
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* cmake:Nicholas Corgan2012-02-281-1/+1
| | | | | | | More git info used for build info UHD version incorporates build info apt/yum repos use new version number New installer filename syntax
* uhd: fixed send pkt handler, vrt packet type was uninitializedJosh Blum2012-02-271-0/+1
| | | | | | | This fixes a bug where the sc8 engine will not interpret the packet as an IF data packet due to uninitialized bits. In that case the sc8 packet would pass through and be interpreted by the downstream as an sc16 packet.
* usrp1: fix to use the db connection type to determine DAC signJosh Blum2012-02-241-2/+10
| | | | | | | | Unlike the other products, usrp1 uses the DAC and not DSP to perform baseband frequency shifting in the hardware. Therefore this shifting occurs before I and Q swapping, and so, the sign of the frequency needs to be inverted on daughterboards which have inverted I and Q TX inputs.
* usrp1: fix advertised samples per packet in send streamerJosh Blum2012-02-211-1/+2
| | | | | Must subtract off the 511 for 512 modulus remainder commit. This bug was introduced by the conversion to streamer API.
* usrp2: some tweaks to the device locking logicJosh Blum2012-02-201-6/+9
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* usrp2: added retry logic to control packetsJosh Blum2012-02-201-2/+32
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* Merge branch 'next'Josh Blum2012-02-1747-344/+1112
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| * dsp rework: fix for vita occ trailer packingJosh Blum2012-02-171-1/+1
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| * dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-152-5/+8
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| * uhd: added async md user payload and common utilsJosh Blum2012-02-144-45/+88
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| * b100: use frame boundary to calculate frame sizeJosh Blum2012-02-142-4/+6
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| * b100: reset/reenumerate fx2 for bad endpoint stateJosh Blum2012-02-143-0/+31
| | | | | | | | | | | | Determine state of control endpoint, re-enumerate to put in a known state, rerun some initialization code.
| * b100: added transport flushes and moved around reset codeJosh Blum2012-02-143-13/+7
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| * dsp rework: minor fix sph, set has time spec for tsf onlyJosh Blum2012-02-141-2/+2
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| * uhd: inline time spec accessors for minor improvementJosh Blum2012-02-131-15/+10
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| * b100/usrp1: various tweaks for compiler warns and valgrindJosh Blum2012-02-094-9/+10
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| * uhd: various tweaks for compiler warns and valgrindJosh Blum2012-02-097-16/+24
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| * uhd: fixed sse2 conversion fc32 to sc8_item32_beJosh Blum2012-02-091-2/+2
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| * uhd: fixed orc conversion fc32 to sc8_item32_beJosh Blum2012-02-091-1/+1
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| * B100: Firmware reset tweaks.Nick Foster2012-02-091-1/+1
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| * uhd: added sse2 conversions for fc32 to sc8Josh Blum2012-02-082-0/+151
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| * uhd: added sse2 conversions for fc64 to sc8Josh Blum2012-02-084-9/+166
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| * Add Orc functions to convert to sc8. bswap version is a bit of a hack.Nick Foster2012-02-082-0/+28
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| * uhd: added sc8 conversion testsJosh Blum2012-02-073-3/+72
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| * dsp rework: implement 64 bit ticks, no secondsJosh Blum2012-02-0616-87/+86
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| * B100: use FPGA external reset on initNick Foster2012-02-062-0/+7
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| * b100/e100: unify rx/tx fifo clears into oneJosh Blum2012-02-044-14/+8
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