| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch addresses issue #648 "B200: TX with SC12 format and MIMO".
The observed MIMO header corruption was caused by overwriting the
end of the packed 12-bit sample output buffer. The overwrite was due to
the converter call always writing out 4 complex samples even if less
than 4 samples were available. The extra samples would corrupt data with
zero padding.
Avoid the overwrite condition by only writing the minimum number of
32-bit lines necessary rather than the entire 12 byte struct.
Samples 32-bit lines
1 1
2 2
3 3
4 3
Signed-off-by: Tom Tsou <tom@tsou.cc>
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* Added CMake toolchain file, compatible with different versions
* No dependency on MinGW runtime, all statically linked
* Misc coding tweaks to allow MinGW to compile
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- Moved setting of tick rate before setting of PPS time
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dboard info for second mboard
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Resolve issue #666 "B200: Rx signal distortion when using SC12".
During 12-bit unpacking, OTW samples are shifted into the high order
bits of the 16-bit intermediate values. The remaining 4-bits are not
zeroed and contain bits from adjacent samples. Consequently, signal
distortion becomes noticable with spurs and other random signal
garbage when operating at low signal levels.
Signed-off-by: Tom Tsou <tom@tsou.cc>
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- X300: FPGA compat 9
- E300: FPGA compat 5
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Conflicts:
host/examples/rx_samples_to_file.cpp
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- Made the methods in adf4001_ctrl virtual
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external ref selection
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- Bugfix for #638
- get_ref_locked will check lock status one last time before giving up
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Our VRT routines have the option to switch, on the fly, between
VRLP and CHDR. This adds new CHDR-specific (un-)packers, which
can only work with CHDR.
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- Deleted images.*, moved functionality to paths.*
- Applies for all devices that check FPGA or FW compat numbers
- Adds generic utility search tool
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Conflicts:
host/lib/usrp/b200/b200_impl.hpp
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- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
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When no master_clock_rate is defined, the B200 driver will now
select a suitable clock rate automatically based on the selected
sampling rate.
The selected tick rate is a multiple of the LCM of tx and rx rates.
Auto-setting is done every time a streamer is generated or the sampling
rate is configured.
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- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
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This is a data type to represent SIDs (stream IDs).
It includes setters and getters for all components of the
SID, converters to and from string and uint32 as well
as C++ streams.
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- Addressed GCC specific errors and warnings
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- Split niriok_proxy interfaces to support NI-RIO <=13.0 and >=14.0 kernel interfaces
- Fixed multi-session race conditions by synchronizing niriok_proxy access
- Fixed bug switching from NI LV-FPGA access to UHD access by changing how devices are hashed into a reservation table
- Fixed calculation of FRAC values for CBX and SBX LO tuning by rounding instead of truncating
- Fixed bug that was not setting two MSBs for band select configuration of CBX LO
- Submitting on behalf of Patrick Sisterhen, Matthew Crymble
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- Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends.
- Bumped FPGA compat number to 8
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