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* usrp1: fix for cordic init, cant do it that way on txJosh Blum2012-02-291-3/+0
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* uhd: fix sc16 to sc8 conversion tableJosh Blum2012-02-291-12/+12
| | | | | | | 1) this was registered as the sc8 to sc16 converter, probably messed that up as well 2) the cast to index was wrong, now unit test passes
* usrp2: device locking tweaksJosh Blum2012-02-291-9/+6
| | | | | | | 1) use bottom bit for force lock condition, that way we never check the time after proper shutdown 2) dont allow lock condition under fpga compat mismatch
* usrp: reset cordics on init after tick rate updateJosh Blum2012-02-284-0/+33
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* uhd: fixed some compile warnings for msvcJosh Blum2012-02-283-3/+3
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* cmake:Nicholas Corgan2012-02-281-1/+1
| | | | | | | More git info used for build info UHD version incorporates build info apt/yum repos use new version number New installer filename syntax
* uhd: fixed send pkt handler, vrt packet type was uninitializedJosh Blum2012-02-271-0/+1
| | | | | | | This fixes a bug where the sc8 engine will not interpret the packet as an IF data packet due to uninitialized bits. In that case the sc8 packet would pass through and be interpreted by the downstream as an sc16 packet.
* usrp1: fix to use the db connection type to determine DAC signJosh Blum2012-02-241-2/+10
| | | | | | | | Unlike the other products, usrp1 uses the DAC and not DSP to perform baseband frequency shifting in the hardware. Therefore this shifting occurs before I and Q swapping, and so, the sign of the frequency needs to be inverted on daughterboards which have inverted I and Q TX inputs.
* usrp1: fix advertised samples per packet in send streamerJosh Blum2012-02-211-1/+2
| | | | | Must subtract off the 511 for 512 modulus remainder commit. This bug was introduced by the conversion to streamer API.
* usrp2: some tweaks to the device locking logicJosh Blum2012-02-201-6/+9
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* usrp2: added retry logic to control packetsJosh Blum2012-02-201-2/+32
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* Merge branch 'next'Josh Blum2012-02-1747-344/+1112
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| * dsp rework: fix for vita occ trailer packingJosh Blum2012-02-171-1/+1
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| * dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-152-5/+8
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| * uhd: added async md user payload and common utilsJosh Blum2012-02-144-45/+88
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| * b100: use frame boundary to calculate frame sizeJosh Blum2012-02-142-4/+6
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| * b100: reset/reenumerate fx2 for bad endpoint stateJosh Blum2012-02-143-0/+31
| | | | | | | | | | | | Determine state of control endpoint, re-enumerate to put in a known state, rerun some initialization code.
| * b100: added transport flushes and moved around reset codeJosh Blum2012-02-143-13/+7
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| * dsp rework: minor fix sph, set has time spec for tsf onlyJosh Blum2012-02-141-2/+2
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| * uhd: inline time spec accessors for minor improvementJosh Blum2012-02-131-15/+10
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| * b100/usrp1: various tweaks for compiler warns and valgrindJosh Blum2012-02-094-9/+10
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| * uhd: various tweaks for compiler warns and valgrindJosh Blum2012-02-097-16/+24
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| * uhd: fixed sse2 conversion fc32 to sc8_item32_beJosh Blum2012-02-091-2/+2
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| * uhd: fixed orc conversion fc32 to sc8_item32_beJosh Blum2012-02-091-1/+1
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| * B100: Firmware reset tweaks.Nick Foster2012-02-091-1/+1
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| * uhd: added sse2 conversions for fc32 to sc8Josh Blum2012-02-082-0/+151
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| * uhd: added sse2 conversions for fc64 to sc8Josh Blum2012-02-084-9/+166
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| * Add Orc functions to convert to sc8. bswap version is a bit of a hack.Nick Foster2012-02-082-0/+28
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| * uhd: added sc8 conversion testsJosh Blum2012-02-073-3/+72
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| * dsp rework: implement 64 bit ticks, no secondsJosh Blum2012-02-0616-87/+86
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| * B100: use FPGA external reset on initNick Foster2012-02-062-0/+7
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| * b100/e100: unify rx/tx fifo clears into oneJosh Blum2012-02-044-14/+8
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| * b100: delete some unused registers from mapJosh Blum2012-02-042-7/+0
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| * dsp rework: move setting address of format registerJosh Blum2012-02-022-6/+4
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| * dsp rework: work on usb wrapper for smaller packets, large lutsJosh Blum2012-02-0215-80/+105
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| * b100: sc8 mode not implemented errorJosh Blum2012-02-011-0/+4
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| * b100: bump compat numbers for slave fifo modeJosh Blum2012-02-011-1/+1
| | | | | | | | | | | | Conflicts: host/lib/usrp/b100/b100_impl.hpp
| * B100: Modified TX send size to achieve 10.7Msps.Nick Foster2012-02-011-1/+1
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| * B100 host code changes to remove TX padding, remove RX padding, increase max ↵Nick Foster2012-02-012-3/+3
| | | | | | | | allowed rate.
| * dsp rework: account for no sid used in tx vita pktJosh Blum2012-02-013-1/+4
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| * dsp rework: tx trailer, scaling work (peak)Josh Blum2012-01-3110-27/+105
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| * gen2: added user setting regs api and user coreJosh Blum2012-01-3113-2/+122
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| * dsp rework: work on scaling and args parsing on RX and TX dspJosh Blum2012-01-317-38/+60
| | | | | | | | | | This simplified some copy pasta in the io_impl.cpp files, and adds a place for sc8 tx mode in the tx dsp core code.
| * dsp rework: implemented new scalefactor in rx dsp coreJosh Blum2012-01-318-19/+32
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| * uhd: implement convert_sc8to_sc16 table w/ scalarJosh Blum2012-01-311-0/+30
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* | usrp1: big endian compile fix, conversion should cast to unsignedJosh Blum2012-02-121-2/+2
| | | | | | | | The htonx only takes unsigned integers, cast the int16 to uint16.
* | windows: do not set process wide priority from thread prioJosh Blum2012-02-081-0/+4
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* | Fixing TX mixer disable, maxing out attenuation when not in use.Ben Hilburn2012-02-072-57/+39
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* | Fixing ADF4351 dividers, even though they won't get used.Ben Hilburn2012-02-071-2/+2
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* | Random formatting while reading through ATR.Ben Hilburn2012-02-071-16/+37
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