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* max287x: assert target_freqMartin Braun2015-10-191-0/+1
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* cbx/sbx: Properly initialize ATR registers during initAshish Chaudhari2015-10-191-0/+3
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* cbx/sbx: Sped up initialization by removing LED blinking sequenceAshish Chaudhari2015-10-191-45/+0
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* usrp3: Added separete caches for GPIO OUT and ATR IDLEAshish Chaudhari2015-10-181-5/+39
| | | | | | - Masking with ATR Disabled deferred to flush - Some dboards like to switch between GPIO and ATR mode and still expect state to be maintained
* fixup! usrp3: Fixed issue where ATR Idle could clobber GPIO outAshish Chaudhari2015-10-161-4/+4
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* Merge branch 'maint'Ashish Chaudhari2015-10-162-4/+37
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| * e3xx: sysfs: Drop reference when we're done.Moritz Fischer2015-10-141-0/+2
| | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * fixup! ad9361: codec manager needs more includes on some platformsMartin Braun2015-10-121-0/+1
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| * B200: Fix for CODEC loopback test failuremichael-west2015-10-121-4/+34
| | | | | | | | - Add delay after putting CODEC in loopback mode
| * b2xx,e3xx,x300: Bumped compat numbers for 3.9.1 UHD releaseAshish Chaudhari2015-09-033-4/+4
| | | | | | | | | | | | | | - b200: compat 11 - b200mini: compat 2 - e300: compat 11 - x300: compat 15
| * b2xx: Removed DCM reset bit (obsolete)Martin Braun2015-09-032-3/+2
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| * b200mini: Change AD9364 interface timing for new IO design.Ian Buckley2015-09-031-17/+3
| | | | | | | | Removes all DCM reset codes.
| * cores: Corrected scaling_adjustment calculationIan Buckley2015-09-034-12/+42
| | | | | | | | | | | | Compensate for headroom required to rotate a signal in the CORDIC. Fixes some CORDIC-related clipping issues, that reduced ENOB to 15 or 14.5 bits.
| * b200: fix startup bad USB state detection printout to use endl instead of ↵Michael Dickens2015-09-021-1/+1
| | | | | | | | flush to print cleanly.
* | fixup! usrp3: Fixed issue where ATR Idle could clobber GPIO outAshish Chaudhari2015-10-161-1/+1
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* | b2xx,e3xx,x300: Bumped compat numbers after GPIO ATR refactoringAshish Chaudhari2015-10-163-4/+4
| | | | | | | | | | | | | | - b200: compat 12 - b200mini: compat 3 - e300: compat 12 - x300: compat 17
* | Merge branch 'ashish/gpio_atr_redux' into master-stagingAshish Chaudhari2015-10-1521-265/+601
|\ \ | | | | | | | | | | | | | | | Conflicts: host/lib/usrp/cores/CMakeLists.txt host/lib/usrp/x300/x300_impl.hpp
| * \ Merge branch 'master' into ashish/gpio_atr_reduxAshish Chaudhari2015-10-154-21/+54
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| * | | usrp3: Fixed issue where ATR Idle could clobber GPIO outAshish Chaudhari2015-10-102-10/+21
| | | | | | | | | | | | | | | | | | | | | | | | - gpio_atr_3000 will not blindly use the mask when writing the ATR and GPIO OUT values. The mask will be ANDed with the value in the ATR Disable register
| * | | usrp3: Added more inline comments to gpio_atr_3000Ashish Chaudhari2015-10-071-5/+31
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| * | | usrp3: Cleaned up some GPIO ATR constants and typesAshish Chaudhari2015-09-302-13/+32
| | | | | | | | | | | | | | | | | | | | - Removed implicit type converstions in ATR address passing - Changed magic numbers to named constants
| * | | usrp3: Added new GPIO ATR 3000 coreAshish Chaudhari2015-09-2921-265/+545
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Refactored GPIO ATR definitions - Added new 3000 core with a more efficient API - Added a separate db_gpio_atr core to control the ATR bus - Ported b2xx, e3xx and x3xx to the new core - Minor cleanup
* | | | Merge branch 'master' into x300/dramAshish Chaudhari2015-10-156-31/+64
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| * | | UBX: Support for Integer-N mode step size controlmichael-west2015-10-151-17/+46
| | | | | | | | | | | | | | | | - Also checks for invalid int_n_step values.
| * | | b200: Updated minimum clock rate to match DCM changesMartin Braun2015-10-143-4/+8
| |/ / | | | | | | | | | | | | | | | Lowest master clock rate is now 220 kHz. At low clock rates, the convergence time for the DC offset and quadrature calibration times is much larger, though.
| * | b200, multi_usrp: More consistent messages regarding auto MCRMartin Braun2015-09-172-10/+10
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* | | fixup! x300: Added DMA FIFO support to X300Ashish Chaudhari2015-09-303-3/+1
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* | | x300: Bumped FPGA compat number to 16Ashish Chaudhari2015-09-161-1/+1
| | | | | | | | | | | | - New and improved DRAM DMA FIFO
* | | x300: Made DRAM FIFO size software configurableAshish Chaudhari2015-09-164-9/+114
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* | | x300: Added DMA FIFO support to X300Ashish Chaudhari2015-09-164-18/+75
| | | | | | | | | | | | | | | - Added HG vs HGS detection logic - Added DMA FIFO configuration code
* | | usrp3: Added AXI DMA FIFO control coreAshish Chaudhari2015-09-163-0/+382
| | | | | | | | | | | | - Can access all registers in axi_dma_fifo.v
* | | usrp3: Added support for pre-FIFO TX flowcontrolAshish Chaudhari2015-09-164-25/+52
|/ / | | | | | | | | | | - tx_vita_core_3000 can now monitor for flow-control immediately before the radio or immediately before the radio external FIFO - B200 does not have an external FIFO so it will use the default config
* | b2xx,e3xx,x300: Bumped compat numbers for 3.9.1 UHD releaseAshish Chaudhari2015-09-083-4/+4
| | | | | | | | | | | | | | - b200: compat 11 - b200mini: compat 2 - e300: compat 11 - x300: compat 15
* | b2xx: Removed DCM reset bit (obsolete)Martin Braun2015-09-082-3/+2
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* | b200mini: Change AD9364 interface timing for new IO design.Ian Buckley2015-09-081-17/+3
| | | | | | | | Removes all DCM reset codes.
* | cores: Corrected scaling_adjustment calculationIan Buckley2015-09-084-12/+42
| | | | | | | | | | | | Compensate for headroom required to rotate a signal in the CORDIC. Fixes some CORDIC-related clipping issues, that reduced ENOB to 15 or 14.5 bits.
* | b200: fix startup bad USB state detection printout to use endl instead of ↵Michael Dickens2015-09-081-1/+1
|/ | | | flush to print cleanly.
* X300: Fix base address for FP GPIOmichael-west2015-09-011-1/+1
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* UHD: Fix max287x N divider rangesmichael-west2015-09-011-5/+5
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* Fixed minor warningsNicholas Corgan2015-09-014-6/+6
| | | | | | * Unreferenced exceptions in try-catch statements * Incorrect function documentation * Unlabelled unused variables
* b200: on startup when the bad USB state is detected, print this out for the ↵Michael Dickens2015-09-011-0/+1
| | | | user to see, with brevity.
* B2XX: Added B200mini supportmichael-west2015-08-1710-92/+277
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* x300: Removed call to is_pps_presentAshish Chaudhari2015-08-171-4/+4
| | | | - It's status is thrown away anyway
* C API: added soft register APINicholas Corgan2015-08-141-0/+48
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* gps_ctrl: code cleanupNicholas Corgan2015-08-141-11/+11
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* multi_usrp: comment out for-now unused function to remove warningNicholas Corgan2015-08-141-2/+2
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* b200,e300,x300: Updated compat number for release 3.9.0Ashish Chaudhari2015-08-143-3/+3
| | | | | | - b200: compat 10 - e300: compat 10 - x300: compat 14
* ad9361: Delay Tx Quad Cal from initialization to streamer startTom Tsou2015-08-131-2/+8
| | | | | | | | | | | | | | | | | | | Patch addresses issue: #742 "tx_waveforms seems to produce unexpectedly large image" Tx Quad Cal performance is temporally dependent with better results when run after the AD9361 is configured for transmission than at initialization. This gets is roughly 5-10 dB of additional quadrature image suppression. Even better performance can be reached when Tx Quad Cal is run after streaming and the AD9361 is actively transmitting. Calibration in this state, however, requires user intervention by retuning the transmit chain by > 100 MHz. Total IQ suppression should be in the range of 40-50+ dBFS dependent on operating frequency. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* ad9361: Use separate Tx and RX frequency calibration intervalsTom Tsou2015-08-132-19/+39
| | | | | | | | | | | | | | | | | | Patch addresses issue: #872 "B200: Tx and Rx calibration share same frequency state" ADI specifies recalibration for certain paths when the LO shifts by more than 100 MHz. Tx and Rx maintain independent LO frequencies so use separate values for determining whether to perform re-calibration at tuning intervals. Also, maintain last calibration frequencies from initialization and clock rate changes. Doing so prevents a re-calibration if the first requested Tx or Rx frequency is close to the default values of 850 and 800 MHz respectively. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* ad9361: Reconfigure RF and baseband DC offset correctionTom Tsou2015-08-132-37/+39
| | | | | | | | | | | | | | | | | | | | | | | | Addressed and related issues: #186 "B200: Catalina RX signal distortion" #821 "Incorrect behavior with auto DC Offset correction turnned off" #820 "Rx DC Offset Correction Convergence on B2xx Dependent on Master Clock Rate" #755 "Demodulate IQ signal amplitude oscillation on B210 at 200 MHz carrier" Due to recent change "ad9361: Invert phase on Rx LNA bypass path", we now have uniform phase alignment across the entire gain range. This drastically improves performance of RF DC tracking - not to be confused with the - active and input dependent - baseband (BB) DC tracking loop. RF DC tracking is not affected by input signals and updates during gain changes. The updated configuration provides improved DC suppression for operation whether BB tracking loop is enabled or disabled. New behavior differs from the previous case where disabling BB tracking would clear all - static and active - calibration tables. Now, static correction tables are not wiped when BB tracking is turned off. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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