| Commit message (Collapse) | Author | Age | Files | Lines |
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None of our FPGA images support a 120 MHz master clock rate, so the UHD
code should match that.
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- Improves performance for frequencies greater than 3.5 GHz
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- This is a combination of 5 commits.
- rh: add lo distribution board gpio expander
- rh: add lo distribution mpm functions
- rh: add code to conditionally initialize lo distribution
- rh: change empty i2c device from exception to assertion
- rh: add lo distribution board control
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Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ni.com>
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EEPROM
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- Limit initialization to ZPU communication if recover_mb_eeprom=1 is
set in device args.
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- This is the only read operation in the driver, so removing it simplifies the
driver's requirements significantly.
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No functional or API changes.
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The sync_source API is an atomic setter for all sync-related settings.
If supported by the underlying USRP, it can be faster to call
set_sync_source() rather than sequentially calling set_clock_source()
and set_time_source().
If the underlying device does not support the sync_source API, it will
fall back to the set_clock_source() and set_time_source() APIs, making
this change backward-compatiple.
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set_time_source() for N310 and N300 can take longer than the default RPC
client timeout of 2 seconds due to dboard initialization.
We need increase this timeout, by using the init timeout value which is
2 minutes.
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After going to 2 radios configuration (FPGA), the channnel value
is passed into this set_rx_antenna now have value either 0 or 1.
We want the mapping of {radio_channel:cpld_channel} = {0:CHAN1} or {1:CHAN2}.
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ALL_MBOARDS and ALL_CHANS will be exported on GCC and MSVC
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This tracks the changes on rx_frontend_gen3.v, which was updated to use
a quarter-rate downconverter instead of a generic CORDIC. The X3x0 FPGA
compat number is incremented as the rx_frontend is part of the device
architecture rather than an RFNoC block.
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The master clock rate was getting overwritten while
running the codec loopback self test. So now we save the
current rate before running the test and then reapply it.
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Clipping requested frequency to acceptable ranges in Magnesium TX/RX
set frequency functions.
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...that are already handled in udp_zero_copy.
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we're no longer need this. Because there are default send buff size in
each transport type impl.
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This is used to determine send_buff_size and recv_buff_size
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The gpio devtest passes after this fix. Enabling the test
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Now matches the FPGA error message (go download, then run
uhd_image_loader).
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- AMP_LO1_EN_CH1 controls U2, the amp for the external LO1 port, so it must
be set high if channel 2 is using an external LO (external or reimport)
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The C/C++ standards don't define what time_t is, only that it is
arithmetic (and real for C11, and integral for C++). It should not be
used in portable software and is only used as the return value for some
libc calls.
A common definition for time_t is int64_t, so we'll switch to that
permanently in our own APIs. System APIs will of course stick with
time_t.
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For USRPs that support user settings (e.g., B2xx, N230), this will
return an object that will allow peeking and poking user-defined
settings registers.
Mock code example:
auto usrp = multi_usrp::make(...);
auto user_settings_iface = usrp->get_user_settings_iface();
user_settings_iface->poke32(0, 23);
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No functional changes. Cleanup only. A little less Boost.
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You can now change the time/clock source default through device args:
auto usrp = uhd::usrp::multi_usrp::make(
"type=x300,clock_source=external,time_source=external");
This also enables the use of config files for the clock/time source
implicitly.
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x300_impl will now use a constrained_device_args_t-derived object to
parse device args.
No API or functional changes.
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Also puts all defaults into the uhd::usrp::x300 namespace.
This commit does some renaming and refactoring, but no functional
changes.
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- Change RX/TX min/max frequency according to AD9361 datasheet
- Fix set_atr_bits to change with rx/tx frequency and antenna independently
- Make AMP switching active high
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- The flushing mechanism now looks similar to that in noc_shell
- Make use of new flush bit in FIFO control register
- Restrict using the clear bit only after flushing to ensure no
partial packets are introduced in the stream. (clear immediately
empties out FIFOs)
- Changes are backwards compatible with older FPGAs
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Before, setting these properties in the prop tree would trigger an
exception.
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This device is the only one using it, and no one will ever use it going
forward.
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- This bug could cause LO to not lock properly after a set_frequency call
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