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* e300: Removed unused constant MAX_TICK_RATEMarcus Müller2015-07-271-1/+0
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* x300: Updated FPGA->ADC Clock delays for all boardsAshish Chaudhari2015-07-241-2/+2
| | | | - Delays changed after ADC config change and FPGA fixes
* b200: Change default tick rate to 16 MHzMartin Braun2015-07-241-1/+1
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* x300: Removed radio_rst assertion codeAshish Chaudhari2015-07-233-3/+4
| | | | | | - radio_rst was being asserted to reset the capture iface IDELAYs but that was excessive and had adverse effects on the rest of the radio - Replaced radio_rst with a localized IDELAYCTRL reset
* Revert "x300: Changed ADC clock swing to 1.6V from 0.7V"Ashish Chaudhari2015-07-231-2/+2
| | | | This reverts commit a12b24027fe1af9ca51949f6a9333ac5451690ef.
* x300: Moved system-level ADC and DAC operationsAshish Chaudhari2015-07-233-386/+413
| | | | | | | | | | | - The following function implementations were moved from x300_impl.cpp to x300_adc_dac_utils.cpp - synchronize_dacs - self_test_adcs - extended_adc_test - self_cal_adc_capture_delay - self_cal_adc_xfer_delay - This reduces the size of the x300_impl object file
* x300: Increased the max image size for burnerAshish Chaudhari2015-07-231-1/+1
| | | | - We added additional microcode to configure DCI matching,config rate,etc
* x300: Updated CLK->DATA delay for ADCAshish Chaudhari2015-07-221-2/+2
| | | | | | | | - The value was originally empirically determined based on self-cal results. After the fix for uncalibrated IDELAY, the self-cal offset data was no longer correct. - The new delay through the ADC ensures that the self-cal nominally pick the halfway tap of 16
* x300: Added a comprehensive radio reset sequenceAshish Chaudhari2015-07-224-32/+68
| | | | | | | | | | | - Everytime the LMK is configured, we do the following: - Reset all LMK regs - Wait for LMK lock - Reset radio_clk PLL in FPGA - Wait for FPGA PLL to lock - Assert radio_rst which resets downstream radio logic - This address the intermittent self-cal failures due to uncalibrated IDELAY taps - Bumped FPGA compat to 12
* x300: Minor: Optimized ADC/DAC resetsAshish Chaudhari2015-07-221-11/+11
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* x300: Changed ADC clock swing to 1.6V from 0.7VAshish Chaudhari2015-07-221-2/+2
| | | | - This changed with the ADS62P44 -> ADS62P48 design change
* ad9361: Updated copyright headersMartin Braun2015-07-216-6/+84
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* Merge branch 'master' into x300/rev7_supportAshish Chaudhari2015-07-201-3/+3
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| * Merge branch 'maint'Martin Braun2015-07-201-3/+3
| |\ | | | | | | | | | | | | Conflicts: host/include/uhd/transport/nirio/nirio_driver_iface.h
| | * e3xx: eeprom: Fix off by one error in serial number writing code.Moritz Fischer2015-07-161-1/+1
| | | | | | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| | * e3xx: Make all e3xx motherboards show up as such.Moritz Fischer2015-07-161-2/+2
| | | | | | | | | | | | | | | | | | | | | All currently available e3xx daugherboards are equivalent from a UHD perspective, so make them consistently show up as "E3XX". Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* | | x300: Addressed code review feedback for Rev7+ supportAshish Chaudhari2015-07-204-129/+137
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* | | x300: Added extended ADC self-testAshish Chaudhari2015-07-192-9/+68
| | | | | | | | | | | | | | | - New device arg "ext_adc_self_test" triggers the test - ext_adc_self_test=<time> runs the test for "time" seconds
* | | x300: Made all X300 revision related errors fatalAshish Chaudhari2015-07-191-13/+20
| | | | | | | | | | | | | | | - product code, revision and revision compat errors are now exceptions - Added recover_mb_eeprom arg to recover from a corrupt/uninitialized EEPROM
* | | x300: Added HW rev compat number supportAshish Chaudhari2015-07-183-13/+40
| | | | | | | | | | | | | | | - Added new field "revision_compat" to mb_eeprom - Enforce a revision_compat of 7
* | | x300: Added new Rev7+ X3x0 MB product codesAshish Chaudhari2015-07-182-2/+54
|/ / | | | | | | | | - Added new PCIe and MB PIDs for new boards - Added an error if MB PID is invalid
* | x300: Bumped max HW rev to 8Martin Braun2015-07-161-1/+1
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* | Added uhd::image_loader class and uhd_image_loader utilityNicholas Corgan2015-07-1523-96/+1468
| | | | | | | | | | | | * Single class for loading firmware/FPGA images onto devices instead of multiple utilities * Loading functions are registered for each device, corresponding to their --args="type=foo" name * Deprecation warnings added to all product-specific image loading utilities
* | Merge branch 'maint'Martin Braun2015-07-141-1/+0
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| * x300: Removed stray debug printMartin Braun2015-07-141-1/+0
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* | Updated compat numbers for B2x0 and X3x0Martin Braun2015-07-142-2/+2
| | | | | | | | | | - B2x0: FW compat number (goes with previous firmware update) - X3x0: Max HW rev number
* | Merge branch 'maint'Martin Braun2015-07-146-25/+46
|\| | | | | | | | | | | | | | | | | | | Conflicts: fpga-src host/CMakeLists.txt host/cmake/Modules/UHDVersion.cmake host/lib/usrp/b200/b200_impl.hpp host/lib/usrp/e300/e300_fpga_defs.hpp host/lib/usrp/x300/x300_fw_common.h
| * x300: Added max hw rev checkingMartin Braun2015-07-142-0/+11
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| * e3xx: Fixup for idle image to follow naming convention.Moritz Fischer2015-07-141-2/+2
| | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * e3xx: Bump compat number from 6 -> 8.Moritz Fischer2015-07-141-1/+1
| | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * e3xx: Increase TX buffer size to PAGE_SIZE.Moritz Fischer2015-07-141-1/+1
| | | | | | | | | | | | | | | | This was originally limited because it performed poor, however, with refactoring that has been done since release, this now gives better performance. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * e3xx: Load idle image on shutdown.Moritz Fischer2015-07-142-23/+33
| | | | | | | | | | | | | | | | | | | | This commit will have UHD load the idle fpga image on destruction of e300_impl. Note: This requires usrp_e310_idle_fpga.bit to be present in the UHD images directory. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * b200: Bumped FPGA compat number to 8 for releaseAshish Chaudhari2015-07-141-1/+1
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* | x300: Added retry mechanism to ADC capture delay self-calAshish Chaudhari2015-07-141-47/+65
| | | | | | | | | | - If the self-cal fails, UHD waits for 2 sec for the ADC temp to stabilize and retries the self-cal
* | x300: Updated pre-rev7 board delays after characterizationAshish Chaudhari2015-07-141-3/+2
| | | | | | | | - Characterized over process and temperature
* | e3xx: Bump compat number to match change on maint.Moritz Fischer2015-07-131-1/+1
| | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* | ad9361: Update Tx Quad Cal to match current gain tablesTom Tsou2015-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes issue #828 "B200: Tx quadrature calibration regression in master" Following commit added new gain table settings to reflect updated values from ADI. Gain indices used by Tx Quad Cal were not matched to accommodate the new tables. 2b06c38 "b2xx: dc offset and iq imbalance correction control" Requirement for Tx Quad Cal is for TIA gain and analog LPF gain to be set at 0 dB, or 0x20 in the gain table. Final effect is a dramatic decrease in Tx DC offset and quadrature image. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* | ad9361: Prevent positive loop gain on Rx quadrature trackingTom Tsou2015-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch fixes a portion of #807 "B210: severe distortion on In-phase data for some gain settings" ADI recommends that the "Prevent Pos Loop Gain" setting be enabled to prevent the Rx quadrature tracking loop from becoming unstable at low power levels. ADI Linux kernel driver also reflects this setting. We do not follow the ADI recommendation. Adjust accordingly. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* | ad9361: Invert phase on Rx LNA bypass pathTom Tsou2015-07-131-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch resolves issue #823 "B200: Receive RF DC calibration makes calibration worse below 34 dB" According to ADI reference documents, enabling any of the 3 LNA's in the receive path causes a 180 degree phase shift. Correspondingly, we invert the LNA bypass path (gain indices below 34 dB) to match. Testing, however, reveals that one of these statements or the polarity inversion setting itself is false. Disabling the switch results in expected behavior and proper phase alignment. Overall effect is up to 60 dB of DC offset suppression ahead of the Rx analog LPF. This reduces the problematic dependency on active baseband tracking and may resolves multiple tracking stability issues. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* | x300: Fixed Windows build issue in x300_clock_ctrlAshish Chaudhari2015-07-091-3/+4
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* | Merge branch 'master' into x300/rev7_supportAshish Chaudhari2015-07-092-3/+3
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| * | Merge branch 'maint'Martin Braun2015-07-082-3/+3
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| | * B200: New AD9361 I/O timing programming to work with new b200_io.v logic design.Ian Buckley2015-07-082-3/+3
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* | | Merge branch 'master' into x300/rev7_supportAshish Chaudhari2015-07-074-34/+39
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| * | Merge branch 'maint'Martin Braun2015-07-011-5/+6
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| | * b200: Codec loopback test now throws on failure.Martin Braun2015-07-011-5/+6
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| | * b200: Modify initialization sequence to avoid warningsMartin Braun2015-06-292-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will set the actual default rate to an integer factor of whatever the tick rate is, but leave the property tree value at zero. This avoids warnings if the chosen tick rate is not a multiple of the previous default rate, but also returns a zero value for the rate when it has not been initialized, allowing the user to probe if the value has not yet been set.
| * | ad9361: brought in Boost.Assign std::map workaround for MSVC 2013Nicholas Corgan2015-06-291-4/+11
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| * | b200: Modify initialization sequence to avoid warningsMartin Braun2015-06-293-25/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will set the actual default rate to an integer factor of whatever the tick rate is, but leave the property tree value at zero. This avoids warnings if the chosen tick rate is not a multiple of the previous default rate, but also returns a zero value for the rate when it has not been initialized, allowing the user to probe if the value has not yet been set.
* | | x300: Added FPGA->ADC Clock delay for rev 7+ boardsAshish Chaudhari2015-07-071-1/+1
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