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* fifo ctrl: implement timed command feature detectionJosh Blum2012-03-232-2/+12
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* fifo ctrl: use regular iface for U2_REG_MISC_CTRL_CLOCKJosh Blum2012-03-231-6/+7
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* fifo ctrl: various tweaksJosh Blum2012-03-233-10/+9
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* fifo ctrl: ~usrp2_fifo_ctrl acks, usrp2 DCM workaround, bootloader no blinkieJosh Blum2012-03-231-0/+8
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* fifo ctrl: spi core work and host implementationJosh Blum2012-03-237-23/+88
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* spi: work on fw support for simple spi coreJosh Blum2012-03-231-2/+2
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* usrp2: permanent timeout increase for timed commandsJosh Blum2012-03-231-2/+6
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* usrp2: implementation of timed commands workingJosh Blum2012-03-234-7/+49
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* usrp2: integrated fifo ctrl into usrp2 modules, implemented window'd ackingJosh Blum2012-03-234-65/+76
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* usrp2: added vrt pack/unpacker to fifo ctrlJosh Blum2012-03-231-33/+46
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* usrp2: host and fw implementation for fifo controlJosh Blum2012-03-236-3/+173
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* usrp2: work on alternative stream destinationJosh Blum2012-03-234-28/+116
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* usrp: fix typo for user setting regJosh Blum2012-03-211-1/+1
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* Disabling the SBX mixer and baseband amp causes griefJason Abele2012-03-161-1/+1
| | | | | Some ADA4927 / AD5380 combinations do not appreciate being disabled, so lets not disable them
* B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the ↵Nick Foster2012-03-161-2/+2
| | | | "stuffing zeroes" problem and improves transport reliability.
* usrp: fix from "rev iq correction"Josh Blum2012-03-163-6/+6
| | | | Must zero out the default IQ correction to have zero effect by default.
* n2x0: adjustment for phase delay over mimo cableJosh Blum2012-03-141-1/+1
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* uhd: rev iq correction numbers formatJosh Blum2012-03-143-47/+10
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* usrp: fix wildcard set for time/clock sourceJosh Blum2012-03-121-2/+2
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* uhd: added fullscale option stream argJosh Blum2012-03-112-0/+4
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* Make DBSRX* set default bandwidth based on codec rateJason Abele2012-03-112-2/+7
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* Fix RSSI measurementJason Abele2012-03-112-18/+4
| | | | | | Improve incorrect calculation in XCVR Remove RFX rssi sensor due to limited dynamic range giving strange results
* usrp1: fix for cordic init, cant do it that way on txJosh Blum2012-02-291-3/+0
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* usrp2: device locking tweaksJosh Blum2012-02-291-9/+6
| | | | | | | 1) use bottom bit for force lock condition, that way we never check the time after proper shutdown 2) dont allow lock condition under fpga compat mismatch
* usrp: reset cordics on init after tick rate updateJosh Blum2012-02-284-0/+33
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* uhd: fixed some compile warnings for msvcJosh Blum2012-02-282-2/+2
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* usrp1: fix to use the db connection type to determine DAC signJosh Blum2012-02-241-2/+10
| | | | | | | | Unlike the other products, usrp1 uses the DAC and not DSP to perform baseband frequency shifting in the hardware. Therefore this shifting occurs before I and Q swapping, and so, the sign of the frequency needs to be inverted on daughterboards which have inverted I and Q TX inputs.
* usrp1: fix advertised samples per packet in send streamerJosh Blum2012-02-211-1/+2
| | | | | Must subtract off the 511 for 512 modulus remainder commit. This bug was introduced by the conversion to streamer API.
* usrp2: some tweaks to the device locking logicJosh Blum2012-02-201-6/+9
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* usrp2: added retry logic to control packetsJosh Blum2012-02-201-2/+32
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* Merge branch 'next'Josh Blum2012-02-1731-223/+502
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| * dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-152-5/+8
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| * uhd: added async md user payload and common utilsJosh Blum2012-02-144-45/+88
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| * b100: use frame boundary to calculate frame sizeJosh Blum2012-02-141-2/+2
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| * b100: reset/reenumerate fx2 for bad endpoint stateJosh Blum2012-02-143-0/+31
| | | | | | | | | | | | Determine state of control endpoint, re-enumerate to put in a known state, rerun some initialization code.
| * b100: added transport flushes and moved around reset codeJosh Blum2012-02-143-13/+7
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| * b100/usrp1: various tweaks for compiler warns and valgrindJosh Blum2012-02-094-9/+10
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| * uhd: various tweaks for compiler warns and valgrindJosh Blum2012-02-096-11/+15
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| * B100: Firmware reset tweaks.Nick Foster2012-02-091-1/+1
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| * dsp rework: implement 64 bit ticks, no secondsJosh Blum2012-02-0613-61/+63
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| * B100: use FPGA external reset on initNick Foster2012-02-062-0/+7
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| * b100/e100: unify rx/tx fifo clears into oneJosh Blum2012-02-044-14/+8
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| * b100: delete some unused registers from mapJosh Blum2012-02-042-7/+0
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| * dsp rework: move setting address of format registerJosh Blum2012-02-022-6/+4
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| * dsp rework: work on usb wrapper for smaller packets, large lutsJosh Blum2012-02-0213-20/+48
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| * b100: sc8 mode not implemented errorJosh Blum2012-02-011-0/+4
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| * b100: bump compat numbers for slave fifo modeJosh Blum2012-02-011-1/+1
| | | | | | | | | | | | Conflicts: host/lib/usrp/b100/b100_impl.hpp
| * B100: Modified TX send size to achieve 10.7Msps.Nick Foster2012-02-011-1/+1
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| * B100 host code changes to remove TX padding, remove RX padding, increase max ↵Nick Foster2012-02-011-1/+1
| | | | | | | | allowed rate.
| * dsp rework: account for no sid used in tx vita pktJosh Blum2012-02-013-1/+4
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