| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Merge branch 'master' into next | Josh Blum | 2012-04-03 | 3 | -4/+10 | |
| |\| | | | | | | | | | | | | | | Conflicts: host/examples/CMakeLists.txt | |||||
| | * | | Merge branch 'maint' | Josh Blum | 2012-03-29 | 3 | -4/+10 | |
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| | | * | usrp1: stop threads in deconstructor | Josh Blum | 2012-03-29 | 3 | -4/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its important to stop the threads before we let the other smart point objects naturally deconstruct to avoid thread-based race conditions. The attempt to deconstruct the tree and soft time ctrl had a bug because the tree had references in subtrees within the dboard manager class. Rather than continue to fix this method and deconstruct the tree to free up soft time ctrl, it seems simpler to just stop the thread in soft time ctrl, and then let it naturally deconstruct later by ref count. | |||||
| * | | | Merge branch 'master' into next | Josh Blum | 2012-03-26 | 3 | -19/+49 | |
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| | * | | Merge branch 'maint' | Josh Blum | 2012-03-26 | 2 | -4/+25 | |
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| | | * | dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHz | Josh Blum | 2012-03-26 | 1 | -1/+8 | |
| | | | | | | | | | | | | | | | | This fixes the lockup/clocking condition when the following hw combo is used: USRP1 r4.5 + DBSRX + another i2c board | |||||
| | | * | usrp2: possible fix for invalid broadcast replies | Josh Blum | 2012-03-26 | 1 | -3/+17 | |
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| | * | | fx2: simplify i2c code and overload eeprom read/write | Josh Blum | 2012-03-26 | 1 | -15/+24 | |
| | | | | | | | | | | | | | | | | Overload eeprom routines to do it in 1 transaction, since default will split it up into many for each byte. | |||||
| * | | | Merge branch 'master' into next | Josh Blum | 2012-03-23 | 1 | -3/+4 | |
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| | * | | Merge branch 'maint' | Josh Blum | 2012-03-23 | 1 | -3/+4 | |
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| | | * | usrp: fix for rx_frontend_core_200 dc offset | Josh Blum | 2012-03-23 | 1 | -3/+4 | |
| | | | | | | | | | | | | | | | | Mask off upper bits when setting a constant offset (I and Q regs). The sign bits (if negative) can flow off into the flags field. | |||||
| * | | | sbx: various fixes and tweaks for locking | Josh Blum | 2012-03-23 | 1 | -4/+3 | |
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| * | | | sbx: mods for PLL sync reset | Josh Blum | 2012-03-23 | 1 | -3/+6 | |
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| * | | | sbx: no readback during tuning, cache lock detect status when read | Josh Blum | 2012-03-23 | 4 | -12/+26 | |
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| * | | | fifo ctrl: code reorganization and integer wrap-around arithmetic | Josh Blum | 2012-03-23 | 1 | -65/+90 | |
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| * | | | fifo ctrl: implement timed command feature detection | Josh Blum | 2012-03-23 | 2 | -2/+12 | |
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| * | | | fifo ctrl: use regular iface for U2_REG_MISC_CTRL_CLOCK | Josh Blum | 2012-03-23 | 1 | -6/+7 | |
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| * | | | fifo ctrl: various tweaks | Josh Blum | 2012-03-23 | 3 | -10/+9 | |
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| * | | | fifo ctrl: ~usrp2_fifo_ctrl acks, usrp2 DCM workaround, bootloader no blinkie | Josh Blum | 2012-03-23 | 1 | -0/+8 | |
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| * | | | fifo ctrl: spi core work and host implementation | Josh Blum | 2012-03-23 | 7 | -23/+88 | |
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| * | | | spi: work on fw support for simple spi core | Josh Blum | 2012-03-23 | 1 | -2/+2 | |
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| * | | | usrp2: permanent timeout increase for timed commands | Josh Blum | 2012-03-23 | 1 | -2/+6 | |
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| * | | | usrp2: implementation of timed commands working | Josh Blum | 2012-03-23 | 4 | -7/+49 | |
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| * | | | usrp2: integrated fifo ctrl into usrp2 modules, implemented window'd acking | Josh Blum | 2012-03-23 | 4 | -65/+76 | |
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| * | | | usrp2: added vrt pack/unpacker to fifo ctrl | Josh Blum | 2012-03-23 | 1 | -33/+46 | |
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| * | | | usrp2: host and fw implementation for fifo control | Josh Blum | 2012-03-23 | 6 | -3/+173 | |
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| * / | usrp2: work on alternative stream destination | Josh Blum | 2012-03-23 | 4 | -28/+116 | |
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| * | usrp: fix typo for user setting reg | Josh Blum | 2012-03-21 | 1 | -1/+1 | |
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| * | Disabling the SBX mixer and baseband amp causes grief | Jason Abele | 2012-03-16 | 1 | -1/+1 | |
| | | | | | | Some ADA4927 / AD5380 combinations do not appreciate being disabled, so lets not disable them | |||||
| * | B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the ↵ | Nick Foster | 2012-03-16 | 1 | -2/+2 | |
| | | | | | "stuffing zeroes" problem and improves transport reliability. | |||||
| * | usrp: fix from "rev iq correction" | Josh Blum | 2012-03-16 | 3 | -6/+6 | |
| | | | | | Must zero out the default IQ correction to have zero effect by default. | |||||
| * | n2x0: adjustment for phase delay over mimo cable | Josh Blum | 2012-03-14 | 1 | -1/+1 | |
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| * | uhd: rev iq correction numbers format | Josh Blum | 2012-03-14 | 3 | -47/+10 | |
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| * | usrp: fix wildcard set for time/clock source | Josh Blum | 2012-03-12 | 1 | -2/+2 | |
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| * | uhd: added fullscale option stream arg | Josh Blum | 2012-03-11 | 2 | -0/+4 | |
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| * | Make DBSRX* set default bandwidth based on codec rate | Jason Abele | 2012-03-11 | 2 | -2/+7 | |
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| * | Fix RSSI measurement | Jason Abele | 2012-03-11 | 2 | -18/+4 | |
| | | | | | | | Improve incorrect calculation in XCVR Remove RFX rssi sensor due to limited dynamic range giving strange results | |||||
| * | usrp1: fix for cordic init, cant do it that way on tx | Josh Blum | 2012-02-29 | 1 | -3/+0 | |
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| * | usrp2: device locking tweaks | Josh Blum | 2012-02-29 | 1 | -9/+6 | |
| | | | | | | | | 1) use bottom bit for force lock condition, that way we never check the time after proper shutdown 2) dont allow lock condition under fpga compat mismatch | |||||
| * | usrp: reset cordics on init after tick rate update | Josh Blum | 2012-02-28 | 4 | -0/+33 | |
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| * | uhd: fixed some compile warnings for msvc | Josh Blum | 2012-02-28 | 2 | -2/+2 | |
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| * | usrp1: fix to use the db connection type to determine DAC sign | Josh Blum | 2012-02-24 | 1 | -2/+10 | |
| | | | | | | | | | Unlike the other products, usrp1 uses the DAC and not DSP to perform baseband frequency shifting in the hardware. Therefore this shifting occurs before I and Q swapping, and so, the sign of the frequency needs to be inverted on daughterboards which have inverted I and Q TX inputs. | |||||
| * | usrp1: fix advertised samples per packet in send streamer | Josh Blum | 2012-02-21 | 1 | -1/+2 | |
| | | | | | | Must subtract off the 511 for 512 modulus remainder commit. This bug was introduced by the conversion to streamer API. | |||||
| * | usrp2: some tweaks to the device locking logic | Josh Blum | 2012-02-20 | 1 | -6/+9 | |
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| * | usrp2: added retry logic to control packets | Josh Blum | 2012-02-20 | 1 | -2/+32 | |
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| * | Merge branch 'next' | Josh Blum | 2012-02-17 | 31 | -223/+502 | |
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| | * | dsp rework: added flusher to vita tx chain on clear | Josh Blum | 2012-02-15 | 2 | -5/+8 | |
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| | * | uhd: added async md user payload and common utils | Josh Blum | 2012-02-14 | 4 | -45/+88 | |
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| | * | b100: use frame boundary to calculate frame size | Josh Blum | 2012-02-14 | 1 | -2/+2 | |
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| | * | b100: reset/reenumerate fx2 for bad endpoint state | Josh Blum | 2012-02-14 | 3 | -0/+31 | |
| | | | | | | | | | | | | | Determine state of control endpoint, re-enumerate to put in a known state, rerun some initialization code. | |||||
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