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* Merging new UHD_IMAGES_DIR utilities and bug fixes.Ben Hilburn2015-01-2710-40/+38
| | | | Also includes NI-USRP Windows Registry Key fixes.
* e300: Bumped FPGA compat number to 6.Ashish Chaudhari2015-01-261-1/+1
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* Merge branch 'maint' into e300/clk_pps_updatesAshish Chaudhari2015-01-263-9/+24
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| * ad9361: Removed unnecessary digital TX attenuationAshish Chaudhari2015-01-231-1/+7
| | | | | | | | | | | | - Fix ported from He. The current TX filter does not need the additional -6dB of headroom. Set it to zero so we meet our max power specs.
| * fixup! ad9361: More check for interpolation/decim ratiosAshish Chaudhari2015-01-231-1/+1
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| * Merge remote-tracking branch 'origin/maint' into ashish/bug672Ashish Chaudhari2015-01-234-7/+1451
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| | * ad9361: More check for interpolation/decim ratiosMartin Braun2015-01-232-7/+16
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| * | b200: Bugfix#672: Enable the correct half-bandsAshish Chaudhari2015-01-211-1/+1
| | | | | | | | | | | | - The control bits for the small and the large half-bands were swapped which would cause the large HB to run too fast. Swapped hb0 and hb1 bits to fix the issue.
* | | e300: Several bugfixes for E300 clk/pps selection codeAshish Chaudhari2015-01-233-26/+6
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* | | e300: UHD support for refclk disciplining using PPS.Ashish Chaudhari2015-01-224-18/+82
| |/ |/| | | | | | | | | - Only supported value for clk_source is internal - time_source automatically changes the disciplining pulse source - Added ref_locked sensor
* | UBX: Add UBX Supportmichael-west2015-01-222-0/+1435
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* ad9361: bugfix for ad9361 gain value truncationJon Kiser2015-01-202-6/+10
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* e300: Changed (max) serial number from 6 to 8.Moritz Fischer2015-01-202-4/+19
| | | | | | | | | | This works without hickup because we store the serial as a \0 terminated string. Note: We now also write the data version fields, as they might come in handy one day. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* B200: Bug #656. Added FIR coeffs for filters with Fs/4 stop band.Ian Buckley2015-01-194-17/+69
| | | | AD9361 driver can now select coeffs for different interpolation ratios.
* e300: Removed duplicate FPGA loading functionMoritz Fischer2015-01-152-31/+0
| | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* b200: Added lo_locked sensorMartin Braun2015-01-143-1/+12
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* e300: rssi sensor network supportJulian Arnold2015-01-124-2/+22
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* b200: rssi sensorJulian Arnold2015-01-121-1/+3
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* ad9361: rssi readoutJulian Arnold2015-01-124-2/+40
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* x300: Fix for BUG #655: X300: Device Time Not Getting Set from GPSDOmichael-west2015-01-121-8/+6
| | | | - Moved setting of tick rate before setting of PPS time
* uhd: Fix for BUG #650: multi_usrp::get_usrp_tx/rx_info returning incorrect ↵michael-west2015-01-121-6/+6
| | | | dboard info for second mboard
* e100: fixed typo in fpga_downloaderNicholas Corgan2015-01-071-2/+2
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* e300,x300: Bumped FPGA compat numberAshish Chaudhari2014-12-162-2/+2
| | | | | - X300: FPGA compat 9 - E300: FPGA compat 5
* e300,x300: Moved LED register space as not to overlap w/ GPIOsAshish Chaudhari2014-12-162-2/+2
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* b200: Fix for PLL setting not being applied intermittentlyAshish Chaudhari2014-12-102-2/+2
| | | | - Made the methods in adf4001_ctrl virtual
* b200: select valid 10 MHz ref (update GPIO) *before* updating ADF4001 ↵Balint Seeber2014-12-081-3/+4
| | | | external ref selection
* x300: Fixed FC window issue (was off by one)Martin Braun2014-12-021-1/+10
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* b200: serialized access to get_rx/tx_streamJulian Arnold2014-11-212-0/+6
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* x300: Clarified FPGA compat error messageMartin Braun2014-11-211-5/+10
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* x300: Cleaned up DAC ctrl and clock init logicAshish Chaudhari2014-11-066-201/+318
| | | | | | | | | | | - DAC: Squashed configuration into 2 main operations: reset and reset_and_resync - DAC: Put in sleep mode during configuration - DAC: Synchronize only if streaming to more than one DAC - DAC: Use falling edge sync mode - DAC: Fixed power up/down settings - DAC: Frontend sync failure is fatal - Clocks: Refactored clock source change logic - Clocks: Cleaned up init and lock-check sequence
* x300: Fixed typo in io_implMartin Braun2014-11-041-1/+1
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* UHD Tune: Clipping RF LO freq to FE's range in MANUAL tune.Ben Hilburn2014-10-291-1/+3
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* MISO and SIMO configurations no longer allowedJulian Arnold2014-10-211-0/+5
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* x300,nirio: Added support for NI-RIO 14.0Ashish Chaudhari2014-10-104-21/+19
| | | | | | | | | - Split niriok_proxy interfaces to support NI-RIO <=13.0 and >=14.0 kernel interfaces - Fixed multi-session race conditions by synchronizing niriok_proxy access - Fixed bug switching from NI LV-FPGA access to UHD access by changing how devices are hashed into a reservation table - Fixed calculation of FRAC values for CBX and SBX LO tuning by rounding instead of truncating - Fixed bug that was not setting two MSBs for band select configuration of CBX LO - Submitting on behalf of Patrick Sisterhen, Matthew Crymble
* x300: Reduced the TX buffer from 576K to 520KAshish Chaudhari2014-10-092-2/+2
| | | | | - Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends. - Bumped FPGA compat number to 8
* e300: Changed TX/RX switch setting in RX only case to improve isolationJonathon Pendlum2014-10-071-2/+2
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* uhd: Improved tuning code and corresponding outputs/warningsBen Hilburn2014-10-071-35/+124
| | | | | * Added convenience function for frequency comparisons * ABI change required
* math: Added a new uhd::math namespace + float comparison routinesBen Hilburn2014-10-074-28/+20
| | | | | * Float comparison is applied to tuning logic in DSP cores. * Properly using INT_MAX/MIN constants, defined in utils/math.hpp
* uhd: fixed RX and TX DSP cores for 3rd generation productsBen Hilburn2014-10-073-29/+52
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* uhd: fixing TX DSP tuning on gen2 devices, special changes for n2xxBen Hilburn2014-10-073-33/+55
| | | | This fixes RX DSP core 200 from tuning outside range and causing overflows.
* significant changes to multi_usrp tuning algorithms - changing DSP tuningBen Hilburn2014-10-071-37/+107
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* Rectifying a great embarassement in UHD. %s/Mhz/MHz.Ben Hilburn2014-10-077-14/+14
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* Initial commit E300 support.Martin Braun2014-10-0734-0/+7080
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* b200: Bumped FX3 firmware compat number to 7.Ashish Chaudhari2014-10-011-1/+1
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* Merge branch 'maint'Martin Braun2014-09-258-55/+177
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| * x300: Reverted back to no analog delay for DAC ref clocksmichael-west2014-09-251-5/+0
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| * x300: added reset and resync of ADCs and DACs when changing reference clockmichael-west2014-09-256-54/+166
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| * B200: added support for reading the exact product name from EEPROM for B200 ↵Neel Pandeya2014-09-251-0/+15
| | | | | | | | and B210
* | Merge branch 'maint'Martin Braun2014-09-243-9/+2
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| * x300: Added output sync for DAC reference clocksMartin Braun2014-09-241-0/+1
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