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- The spectral distortion was begin caused by the DAC FIFO
underflowing. The fix was to run through the DAC sync
procedure which uses the falling edge clock to sample
the RefClk and sync it with the data clk
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- If there were duplicate IPs in the mboard eeprom, the last one would be selected instead of the first
- The default IP addresses (used for the case where the mboard eeprom can't be read) would overwrite the previous settings
- Added a warning for duplicate IP entries in the mboard eeprom
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- This change ensures that the smallest frame size is chosen with dual ethernet
- It helps avoid any issues with using frame sizes larger than what the smaller link supports
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- A dboard_base class can have multiple frontends (subdevs) and
the set_fe_connection needs to be able to distinguish between them
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- Fixed an issue where 10GE on the HGS image presented a false warning for the link capacity
- Removed some unnecessary variables after cleanup
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Conflicts:
host/CMakeLists.txt
host/lib/usrp/b200/b200_impl.cpp
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Conflicts:
fpga-src
host/cmake/Modules/UHDVersion.cmake
host/lib/usrp/b200/b200_impl.cpp
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DSP rates are now being tracked as in whether or not they've been set.
We can disregard unset DSPs for the automatic clock rate calculation.
Reviewed-By: Derek Kozel <derek.kozel@ettus.com>
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Kernels (3.15+) introduce the possibility to do DUAL and QUAD spi
operations via spidev.
Prior to this commit nothing was setting the {tx,rx}_nbits members
of the struct spi_ioc_transfer.
from include/uapi/linux/spi/spidev.h
struct spi_ioc_transfer {
__u64 tx_buf;
__u64 rx_buf;
__u32 len;
__u32 speed_hz;
__u16 delay_usecs;
__u8 bits_per_word;
__u8 cs_change;
__u8 tx_nbits;
__u8 rx_nbits;
__u16 pad;
};
This turns into an issue on more recent kernels,
where it turns all transactions into QUAD transactions,
while the controller actually doesn't support that mode of
operation.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Conflicts:
host/lib/usrp/cores/gpio_core_200.cpp
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- Updated images
- E310: Bumped compat number to 16 for radio reset fix
- Update fpga-src submodule pointer
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- rx_dsp_core: set_mux takes in a fe_connection obj
to determine IQ mapping and sampling mode parameters
- rx_dsp_core: Support a non-zero IF for downconversion
The current strategy applies a software DSP freq offset
which eats into the range of the CORDIC which is OK
because heterodyne assumes real-mode sampling
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- Wraps a sampling mode and IF frequency
- Built-in parser to deduce swap,invert,mode bits from string connection
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* Removed code referencing now-unsupported versions of Boost
* Added <stdint.h> includes where needed
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* nirio_driver_iface_win: labeled unused variable for MinGW builds
* b200_impl: fixed unreferenced variable warning
* n200_image_loader: fixed signed vs. unsigned comparison
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When querying temp mboard sensor on e300, sysfs attributes are read
through udev.
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Window's WinUSB driver doesn't support multiple processes accessing a
single USB device and libusb_open returns LIBUSB_ACCESS_ERROR when
trying to access an already claimed USRP. One device access did not
catch this exception and caused UHD to error during USRP discovery.
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- The typical dboard classes are actually "subdev" classes i.e.
there is one instance per dboard subdev (front-end). This makes
it hard to implement shared functionality between multiple
front-ends.
- This changes adds the ability to create a container class which
is created per group of subdevs and each subdev gets a pointer
to the container class for cross linkage.
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- Interface and all base classes have virtual destructors
- Wrapped UBX dtor in UHD_SAFE_CALL
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Conflicts:
host/lib/usrp/cores/gpio_core_200.cpp
host/lib/usrp/dboard/db_ubx.cpp
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- Disabled MAX2871 VCO auto selection for phase sync
- Added checks for new phase sync constraints recently published by Maxim
- Added dboard_clock_rate option for X300
- Adjusted timing of SYNC signal relative to dboard referenc clock
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- DB connection mapping is implemented in DDC chain. FE corrections module does not swap
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- Made dboard_iface an interface! Removed PIMPL
- Added unit "BOTH" to dboard API and expanded GPIO API width to 32
- Removed gpio_debug_mux. No product ever used that
- Refactored gpio_atr cores to work with new dboard_iface
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- Moved dboard iface initialization to dboard_manager
- Added a restricted register function. Restricted dboards
don't expose their control iface in the property tree
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- Removed adf435x_common and replaced with a real encapsulated interface
- Looks similar to the MAX287X code
- Updated all DB classes to use the new common code
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- Added desired and coerced values and accessors to property
- Added support to register desired subscribers
- set APIs don't reallocate storage for a property value
- Renamed callback method registration APIs
- Registering 2 coercers or publishers for a property will throw
- Registering a coercer and a publisher for the same property will throw
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