| Commit message (Collapse) | Author | Age | Files | Lines |
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This was originally limited because it performed poor,
however, with refactoring that has been done since release,
this now gives better performance.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This commit will have UHD load the idle fpga image on
destruction of e300_impl.
Note: This requires usrp_e310_idle_fpga.bit to be present
in the UHD images directory.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- If the self-cal fails, UHD waits for 2 sec for the ADC temp
to stabilize and retries the self-cal
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- Characterized over process and temperature
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Fixes issue #828 "B200: Tx quadrature calibration regression in master"
Following commit added new gain table settings to reflect updated values
from ADI. Gain indices used by Tx Quad Cal were not matched to
accommodate the new tables.
2b06c38 "b2xx: dc offset and iq imbalance correction control"
Requirement for Tx Quad Cal is for TIA gain and analog LPF gain to be
set at 0 dB, or 0x20 in the gain table. Final effect is a dramatic
decrease in Tx DC offset and quadrature image.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Patch fixes a portion of #807
"B210: severe distortion on In-phase data for some gain settings"
ADI recommends that the "Prevent Pos Loop Gain" setting be enabled to
prevent the Rx quadrature tracking loop from becoming unstable at low
power levels. ADI Linux kernel driver also reflects this setting.
We do not follow the ADI recommendation. Adjust accordingly.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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This patch resolves issue #823
"B200: Receive RF DC calibration makes calibration worse below 34 dB"
According to ADI reference documents, enabling any of the 3 LNA's in the
receive path causes a 180 degree phase shift. Correspondingly, we invert
the LNA bypass path (gain indices below 34 dB) to match. Testing,
however, reveals that one of these statements or the polarity inversion
setting itself is false. Disabling the switch results in expected
behavior and proper phase alignment.
Overall effect is up to 60 dB of DC offset suppression ahead of the Rx
analog LPF. This reduces the problematic dependency on active baseband
tracking and may resolves multiple tracking stability issues.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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This will set the actual default rate to an integer factor
of whatever the tick rate is, but leave the property tree
value at zero. This avoids warnings if the chosen tick rate
is not a multiple of the previous default rate, but also
returns a zero value for the rate when it has not been
initialized, allowing the user to probe if the value has not
yet been set.
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This will set the actual default rate to an integer factor
of whatever the tick rate is, but leave the property tree
value at zero. This avoids warnings if the chosen tick rate
is not a multiple of the previous default rate, but also
returns a zero value for the rate when it has not been
initialized, allowing the user to probe if the value has not
yet been set.
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- Self-calibration routine steps through various values of IDELAY
taps on the SS data bits to detect metastability in the capture interface
and computes an ideal delay tap value
- Self calibration is triggered at device creation
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- Self-calibration routine steps through various values of LMK
delay to detect metastability in the SSCLK -> radio_clk crossing
and computes an ideal delay for the ADC clock.
- Self calibration is triggered at startup if the self_cal_adc_delay
device arg is specified
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- This function allows delaying divider pairs using the digital and analog
delay blocks in the LMK divider
- ctrl object caches delay for later retrieval
- Minor fixes to LMK regmap
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Conflicts:
host/lib/usrp/common/ad9361_ctrl.hpp
host/lib/usrp/common/ad9361_driver/ad9361_device.h
host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
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When the LO is tuned it changes the frequency on both channels. The frequency value read back for the first channel was not updated when the LO frequency for the other channel was tuned to a different value.
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
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Max rate is now set to 53248000, allowing for more than 8MS/s,
which is closer to the actual value that USB2 can handle.
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This is a change from behaviour so far. Before the GPS was only
on while UHD is running. This behaviour was confusing users,
and didn't match our other devices.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Before the device time wasn't set for E310 on initialization.
This will allow 'query_gpsdo_sensors' to pass if gps has lock.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Conflicts:
fpga-src
host/CMakeLists.txt
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When auto tick rate is used, and the sampling rate exceeds the
limits, throw an error instead of coercing to the default rate.
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